Described are microelectronic devices comprising a dielectric layer formed on a substrate, a feature comprising a gap defined in the dielectric layer, a barrier layer on the dielectric layer, a two metal liner film on the barrier layer and a gap fill metal on the two metal liner. Embodiments provide a method of forming a microelectronic device comprising the two metal liner film on the barrier layer.

A hybrid wafer bonding method includes providing a first semiconductor structure and providing a second semiconductor structure. The first semiconductor structure includes a first substrate, a first dielectric, and a first via structure. The first via structure includes a first contact via and first metal impurities doped in the first contact via. The second semiconductor structure includes a second substrate, a second dielectric layer, and a second via structure. The second via structure includes a second contact via and second metal impurities doped in the second contact via. The method further includes bonding the first semiconductor structure with the second semiconductor and forming a self-barrier layer by an alloying process. The self-barrier layer is formed by a multi-component oxide corresponding to the first and second metal impurities.

A method and a structure for determining a blocking ability of a copper diffusion blocking layer are disclosed. The method includes: a step S1 of forming an a-Si semiconductor layer, the copper diffusion blocking layer, and a copper electrode layer on a glass substrate; a step S2 of forming a transparent electrode layer on the glass substrate; a step S3 of performing a high temperature deterioration process to the glass substrate; and a step S4 of observing a degree of forming the black copper-silicon alloy layer on a surface of a composite film layer sample of the glass substrate.

In a contact hole of an interlayer insulating film, a tungsten film forming a contact plug is embedded via a barrier metal. The interlayer insulating film is formed by sequentially stacked HTO and BPSG films. The BPSG film has an etching rate faster than that of the HTO film with respect to a hydrofluoric acid solution used in wet etching of preprocessing before formation of the barrier metal. After the contact hole is formed in the interlayer insulating film, a width of an upper portion of the contact hole at the BPSG film is increased in a step-like shape, to be wider than a width of a lower portion at the HTO film by the wet etching before the formation of the barrier metal, whereby an aspect ratio of the contact hole is reduced. Thus, size reductions and enhancement of the reliability may be realized.

A hybrid wafer bonding method includes providing a first semiconductor structure and providing a second semiconductor structure. The first semiconductor structure includes a first via structure in a first dielectric layer, the first via structure including a first contact via surface. The second semiconductor structure includes a second via structure in a second dielectric layer, the second via structure including a second contact via surface. The first contact via surface is bonded with the second contact via surface. A barrier structure is formed surrounding the second contact via surface along a lateral direction and extending into each of the first contact via surface and the second dielectric layer in a vertical direction. The first via structure includes first metal impurities doped in a bulk region of the first via structure, and the second via structure includes second metal impurities doped in a bulk region of the second via structure.

A process for forming cobalt on a substrate, comprising: volatilizing a cobalt precursor of the disclosure, to form, a precursor vapor: and contacting the precursor vapor with the substrate under vapor deposition conditions effective for depositing cobalt on the substrate from the precursor vapor, wherein the vapor deposition conditions include temperature not exceeding 200° C., wherein: the substrate includes copper surface and dielectric material, e.g., ultra-low dielectric material. Such cobalt deposition process can be used to manufacture product articles in which the deposited cobalt forms a capping layer, encapsulating layer, electrode, diffusion layer, or seed for electroplating of metal thereon, e.g., a semiconductor device, flat-panel, display, or solar panel. A cleaning composition containing base and oxidizing agent components may be employed to clean the copper prior to deposition of cobalt thereon, to achieve substantially reduced defects in the deposited cobalt.

An integrated circuit device includes a metal film and a complex capping layer covering a top surface of the metal film. The metal film includes a first metal, and penetrates at least a portion of an insulating film formed over a substrate. The complex capping layer includes a conductive alloy capping layer covering the top surface of the metal film, and an insulating capping layer covering a top surface of the conductive alloy capping layer and a top surface of the insulating film. The conductive alloy capping layer includes a semiconductor element and a second metal different from the first metal. The insulating capping layer includes a third metal.

A vertical semiconductor device may include a semiconductor substrate having at least one trench therein, and a superlattice layer extending vertically adjacent the at least one trench. The superlattice layer may comprise stacked groups of layers, with each group of layers comprising stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer. Each at least one non-semiconductor monolayer of each group of layers may be constrained within a crystal lattice of adjacent base semiconductor portions. The vertical semiconductor device may also include a doped semiconductor layer adjacent the superlattice layer, and a conductive body adjacent the doped semiconductor layer on a side thereof opposite the superlattice layer and defining a vertical semiconductor device contact.

A process of smoothing a top surface of a bit line metal of a memory structure to decrease resistance of a bit line stack. The process includes depositing titanium layer of approximately 30 angstroms to 50 angstroms on polysilicon layer on a substrate, depositing first titanium nitride layer of approximately 15 angstroms to approximately 40 angstroms on titanium layer, annealing substrate at a temperature of approximately 700 degrees Celsius to approximately 850 degrees Celsius, depositing second titanium nitride layer of approximately 15 angstroms to approximately 40 angstroms on first titanium nitride layer after annealing, depositing a bit line metal layer of ruthenium on second titanium nitride layer, annealing bit line metal layer at temperature of approximately 550 degrees Celsius to approximately 650 degrees Celsius, and soaking bit line metal layer in hydrogen-based ambient for approximately 3 minutes to approximately 6 minutes during annealing.

A method and structure for forming an enhanced metal capping layer includes forming a portion of a multi-level metal interconnect network over a substrate. In some embodiments, the portion of the multi-level metal interconnect network includes a plurality of metal regions. In some cases, a dielectric region is disposed between each of the plurality of metal regions. By way of example, a metal capping layer may be deposited over each of the plurality of metal regions. Thereafter, in some embodiments, a self-assembled monolayer (SAM) may be deposited, where the SAM forms selectively on the metal capping layer, while the dielectric region is substantially free of the SAM. In various examples, after selectively forming the SAM on the metal capping layer, a thermal process may be performed, where the SAM prevents diffusion of the metal capping layer during the thermal process.