To provide a semiconductor device that has barrier metal and has a small variation in a threshold voltage. A semiconductor device is provided, including a semiconductor substrate, an interlayer dielectric film arranged on an upper surface of the semiconductor substrate, a titanium layer provided on the interlayer dielectric film, and a titanium nitride layer provided on the titanium layer, where the interlayer dielectric film is provided with an opening that exposes a part of the upper surface of the semiconductor substrate, the titanium layer and the titanium nitride layer are also provided within the opening, and the titanium layer arranged in contact with the semiconductor substrate and on a bottom portion of the opening is entirely titanium-silicided.

A method includes forming a trench within a dielectric layer, the trench comprising an interconnect portion and a via portion, the via portion exposing an underlying conductive feature. The method further includes depositing a seed layer within the trench, depositing a carbon layer on the seed layer, performing a carbon dissolution process to cause a graphene layer to form between the seed layer and the underlying conductive feature, and filling a remainder of the trench with a conductive material.

Embodiments of the present disclosure are related to improved methods for forming an interconnect structure in a substrate. In one implementation, the method includes providing a substrate comprising a metal region and a dielectric region surrounding the metal region, selectively forming a cobalt-containing alloy cap layer on the metal region by exposing the substrate to a first precursor and a second precursor, the first precursor and the second precursor are selected from a group consisting of an aluminum-containing precursor, a cobalt-containing precursor, a ruthenium-containing precursor, a manganese-containing precursor, and a tungsten-containing precursor, wherein the first precursor is different from the second precursor.

A method of forming a composite crystalline nitride structure is provided. The method includes depositing a first crystalline nitride layer on a substrate, patterning the first crystalline nitride layer to form a patterned crystalline nitride layer having a top surface and that includes undulations, annealing the patterned crystalline nitride layer at a temperature between 300° C. to 850° C. to form an annealed patterned crystalline nitride layer, and depositing a second crystalline nitride layer on the annealed patterned crystalline nitride layer. The second crystalline nitride layer is lattice-matched to the underlying annealed patterned crystalline nitride layer to within 2%, thereby forming the composite crystalline nitride structure.

A device relates to a semiconductor device. The semiconductor device includes a narrow-line bamboo microstructure integrated within a metal layer of the semiconductor device and a narrow-line polycrystalline microstructure. The narrow-line polycrystalline microstructure is integrated within the same metal layer as the narrow-line bamboo microstructure.

A method of forming an electronic device is disclosed. The method comprises forming depositing a metal on a substrate, the metal comprising one or more of copper (Cu), titanium (Ti), or tantalum (Ta). A metal cap is deposited on the metal. The metal cap comprises one or more of molybdenum (Mo), ruthenium (Ru), iridium (Ir), rhodium (Rh), palladium (Pd), silver (Ag), osmium (Os), platinum (Pt), or gold (Au). The substrate is then exposed to an anneal process, e.g., a hydrogen high-pressure anneal. The formation of the metal cap on the metal minimizes parasitic adsorption of hydrogen by the underlying metal.

An IC structure includes a transistor, a source/drain contact, a metal oxide layer, a non-metal oxide layer, a barrier structure, and a via. The transistor includes a gate structure and source/drain regions on opposite sides of the gate structure. The source/drain contact is over one of the source/drain regions. The metal oxide layer is over the source/drain contact. The non-metal oxide layer is over the metal oxide layer. The barrier structure is over the source/drain contact. The barrier structure forms a first interface with the metal oxide layer and a second interface with the non-metal oxide layer, and the second interface is laterally offset from the first interface. The via extends through the non-metal oxide layer to the barrier structure.

A method for filling recessed features with a low-resistivity metal includes providing a patterned substrate containing a recessed feature formed in a first layer and a second layer that is exposed in the recessed feature, pre-treating the substrate with a surface modifier that increases metal deposition selectivity on the second layer relative to on the first layer, and depositing a metal layer on the substrate by vapor phase deposition, where the metal layer is preferentially deposited on the second layer in the recessed feature. The method further includes removing metal nuclei deposited on the first layer, including on a field area and on sidewalls of the first layer in the recessed feature, to selectively form the metal layer on the second layer in the recessed feature, where the removing includes exposing the patterned substrate to an etching gas containing ozone.

Methods of forming devices comprise forming a dielectric layer on a substrate, the dielectric layer comprising at least one feature defining a gap including sidewalls and a bottom. The methods include selectively depositing a self-assembled monolayer (SAM) on the bottom of the gap. The SAM comprises a hydrocarbon having a formula of H—C≡C—R, wherein R is a linear alkyl chain or aryl group comprising from 1 to 20 carbon atoms or a formula of R′C═CR″, wherein R′ and R″ independently include a linear alkyl chain or aryl group comprising from 1 to 20 carbon atoms A barrier layer is formed on the SAM before selectively depositing a metal liner on the barrier layer. The SAM is removed after selectively depositing the metal liner on the barrier layer.

A method includes forming a trench within a dielectric layer, the trench comprising an interconnect portion and a via portion, the via portion exposing an underlying conductive feature. The method further includes depositing a seed layer within the trench, depositing a carbon layer on the seed layer, performing a carbon dissolution process to cause a graphene layer to form between the seed layer and the underlying conductive feature, and filling a remainder of the trench with a conductive material.