Described are methods for doping barrier layers such as tantalum (Ta), tantalum nitride (TaN), tantalum carbide (TaC), niobium (Nb), niobium nitride (NbN), manganese (Mn), manganese nitride (MnN), titanium (Ti), titanium nitride (TiN), molybdenum (Mo), and molybdenum nitride (MoN), and the like. Dopants may include one or more of one or more of ruthenium (Ru), manganese (Mn), niobium (Nb), cobalt (Co), vanadium (V), copper (Cu), aluminum (Al), carbon (C), oxygen (O), silicon (Si), molybdenum (Mo), and the like. The doped barrier layer provides improved adhesion at a thickness of less than about 15 Å.

Described are microelectronic device comprising a dielectric layer formed on a substrate, a feature 206 comprising a gap defined in the dielectric layer, a barrier layer on the dielectric layer, a two metal liner film on the barrier layer and a gap fill metal on the two metal liner. Embodiments provide a method of forming an microelectronic device comprising the two metal liner film on the barrier layer.

According to various embodiments, a device may include: a semiconductor region; a metallization layer disposed over the semiconductor region; and a self-organizing barrier layer disposed between the metallization layer and the semiconductor region, wherein the self-organizing barrier layer comprises a first metal configured to be self-segregating from the metallization layer.

In a contact hole of an interlayer insulating film, a tungsten film forming a contact plug is embedded via a barrier metal. The interlayer insulating film is formed by sequentially stacked HTO and BPSG films. The BPSG film has an etching rate faster than that of the HTO film with respect to a hydrofluoric acid solution used in wet etching of preprocessing before formation of the barrier metal. After the contact hole is formed in the interlayer insulating film, a width of an upper portion of the contact hole at the BPSG film is increased in a step-like shape, to be wider than a width of a lower portion at the HTO film by the wet etching before the formation of the barrier metal, whereby an aspect ratio of the contact hole is reduced. Thus, size reductions and enhancement of the reliability may be realized.

A method of forming a contact to a semiconductor device is provided that forms an alloy composed of nickel (Ni), platinum (Pt), aluminum (Al), titanium (Ti) and a semiconductor material. The methods may include forming a nickel and platinum semiconductor alloy at a base of a via. A titanium layer having an angstrom scale thickness is deposited in the via in contact with the nickel platinum semiconductor alloy. An aluminum containing fill is deposited atop the titanium layer. A forming gas anneal including an oxygen containing atmosphere is applied to the structure to provide a contact alloy comprising nickel, platinum, aluminum, titanium and a semiconductor element from the contact surface of the semiconductor device.

The semiconductor structure includes a substrate; a dielectric layer formed on the substrate; an opening, formed through the dielectric layer; a contact layer formed at bottom of the opening; a blocking layer formed on a sidewall surface of the opening; and a plug formed in the opening. The plug is formed on a sidewall surface of the blocking layer and in contact with the contact layer.

An etch back air gap (EBAG) process is provided. The EBAG process includes forming an initial structure that includes a dielectric layer disposed on a substrate and a liner disposed to line a trench defined in the dielectric layer. The process further includes impregnating a metallic interconnect material with dopant materials, filling a remainder of the trench with the impregnated metallic interconnect materials to form an intermediate structure and drive-out annealing of the intermediate structure. The drive-out annealing of the intermediate structure serves to drive the dopant materials out of the impregnated metallic interconnect materials and thereby forms a chemical- and plasma-attack immune material.

The present invention relates to an electrolyte and its use in a process for fabricating copper interconnects. The electrolyte of pH greater than 6.0 comprises copper ions, manganese or zinc ions, and ethylenediamine which complexes the copper. A thin barrier layer is formed by annealing the deposited copper alloy, which causes manganese or zinc to migrate to the interface between the insulating dielectric material and the copper.

An integrated circuit has a first layer having a recess that extends into the first layer. In addition, a second layer is within the recess and comprises a metal or a dielectric, and a third layer is within the recess and between the first and second layers, the third layer including a material that resonates at microwave frequencies (e.g., 2.4 GHz to 2.5 GHz). In some cases, the third layer material includes: (1) oxygen along with indium and/or zinc; or (2) diethylene glycol dibenzoate. In some cases, such as where the first layer comprises a dielectric (e.g., silicon dioxide) and second layer comprises a metal (e.g., copper), the integrated circuit further includes a fourth layer (e.g., barrier layer including tantalum or titanium) between the second and third layers. The third layer resonates in response to microwave annealing, thereby selectively heating the second layer (e.g., to reflow and/or grow grain size).

A method for preparing a semiconductor device structure includes forming a first dielectric layer over a semiconductor substrate; forming a first conductive plug in the first dielectric layer; forming a polysilicon layer covering the first dielectric layer and the first conductive plug; transforming a portion of the polysilicon layer into a silicide portion; forming a second conductive plug directly over the silicide portion; and forming a second dielectric layer surrounding the second conductive plug.