A transistor, integrated semiconductor device and methods of making are provided. The transistor includes a dielectric layer having a plurality of dielectric protrusions, a channel layer conformally covering the protrusions of the dielectric layer to form a plurality of trenches between two adjacent dielectric protrusion, a gate layer disposed on the channel layer. The gate layer 106 has a plurality of gate protrusions fitted into the trenches. The transistor also includes active regions aside the gate layer. The active regions are electrically connected to the channel layer.

An integrated circuit includes a first nanostructure transistor including a plurality of first semiconductor nanostructures over a substrate and a source/drain region in contact with each of the first semiconductor nanostructures. The integrated circuit includes a second nanostructure transistor including a plurality of second semiconductor nanostructures and a second source/drain region in contact with one or more of the second semiconductor nanostructures but not in contact with one or more other second semiconductor nanostructures.

A semiconductor structure and a method for manufacturing the semiconductor structure are provided. The method includes: providing a substrate including a core NMOS area, a core PMOS area and a peripheral NMOS area; performing oxidation treatment on the substrate in the core PMOS area to convert a thickness of a part of the substrate in the core PMOS area into an oxide layer; removing the oxide layer; forming a first semiconductor layer on the remaining substrate in the core PMOS area; forming a gate dielectric layer located on the first semiconductor layer and on the substrate in the core NMOS area and the peripheral NMOS area; and forming a gate on the gate dielectric layer.

Techniques herein include methods of forming channel structures for field effect transistors having a channel current path parallel to a surface of a substrate. 3D in-situ horizontal or lateral growth of the channel and source/drain regions allows for a custom doping in the 3D horizontal nanosheet direction for NMOS and PMOS devices. An ultra-short channel length is achieved with techniques herein because the channel is epitaxially grown in the 3D horizontal nanosheet direction at the monolayer level. Since the channel is grown in a dielectric cavity, a precise channel cross sectional area can be tuned.

The present disclosure describes a semiconductor device with substantially uniform gate regions and a method for forming the same. The method includes forming a fin structure on a substrate, the fin structure including one or more nanostructures. The method further includes removing a portion of the fin structure to expose an end of the one or more nanostructures and etching the end of the one or more nanostructures with one or more etching cycles. Each etching cycle includes purging the fin structure with hydrogen fluoride (HF), etching the end of the one or more nanostructures with a gas mixture of fluorine (F.sub.2) and HF, and removing an exhaust gas mixture including an etching byproduct. The method further includes forming an inner spacer in the etched end of the one or more nanostructures.

An integrated circuit includes a first nanostructure transistor having a first gate electrode and a second nanostructure transistor having a second gate electrode. A dielectric isolation structure is between the first and second gate electrodes. A gate connection metal is on a portion of the top surface of the first gate electrode and on a portion of a top surface of the second gate electrode. The gate connection metal is patterned to expose other portions of the top surfaces of the first and second gate electrodes adjacent to the dielectric isolation structure. A conductive via contacts the exposed portion of the top surface of the second gate electrode.

A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a base and a fin structure over the base. The semiconductor device structure includes an isolation structure over the base and surrounding a lower portion of the fin structure. The semiconductor device structure includes a gate stack wrapped around an upper portion of the fin structure. The semiconductor device structure includes a source/drain structure partially embedded in the isolation structure and the lower portion of the fin structure. The source/drain structure has an undoped semiconductor layer and a first doped layer over the undoped semiconductor layer, and the undoped semiconductor layer separates the first doped layer from the isolation structure.

The present disclosure provides a semiconductor structure and a manufacturing method thereof. The manufacturing method includes: depositing a thin-film stacked structure on a substrate; forming a first hole in the thin-film stacked structure; growing an epitaxial silicon pillar in the first hole; etching the thin-film stacked structure and the epitaxial silicon pillar along a first direction to form a first trench, the first trench passing through a center of the epitaxial silicon pillar and dividing the epitaxial silicon pillar into a first half pillar and a second half pillar; forming a first isolation layer; forming a first channel region of a first doping type, and forming a second channel region of a second doping type; and forming a gate dielectric layer and a gate conductive layer on a surface of each of the first channel region and the second channel region.

To further reduce contact resistance when a current or a voltage is taken out from a metal layer. A conductive structure including: an insulating layer; a metal layer provided on one surface of the insulating layer to protrude in a thickness direction of the insulating layer; and a two-dimensional material layer provided along outer shapes of the metal layer and the insulating layer from a side surface of the metal layer to the one surface of the insulating layer.

A semiconductor structure is provided. The semiconductor structure includes nanostructures stacked over a substrate and spaced apart from one another, gate dielectric layers wrapping around the nanostructures respectively, nitride layers wrapping around the gate dielectric layers respectively, oxide layers wrapping around the nitride layers respectively, work function layers wrapping around the oxide layers respectively, and a metal fill layer continuously surrounding the work function layers.