The present disclosure provides a method of forming N-type and P-type source/drain features using one patterned mask and one self-aligned mask to increase windows of error tolerance and provide flexibilities for source/drain features of various shapes and/or volumes. The present disclosure also includes forming a trench between neighboring source/drain features to remove bridging between the neighboring source/drain features. In some embodiments, the trenches between the source/drain features are formed by etching from the backside of the substrate.

The present disclosure provides embodiments of semiconductor structures and method of forming the same. An example semiconductor structure includes a first source/drain feature and a second source/drain feature and a hybrid fin disposed between the first source/drain feature and the second source/drain feature and extending lengthwise along a first direction. The hybrid fin includes an inner feature and an outer layer disposed around the inner feature. The outer layer includes silicon oxycarbonitride and the inner feature includes silicon carbonitride.

A semiconductor device capable of improving operation performance and reliability, may include a gate insulating support to isolate gate electrodes that are adjacent in a length direction. The semiconductor device includes a first gate structure on a substrate, the first gate structure extending lengthwise in a first direction to have two long sides and two short sides, relative to each other, and including a first gate spacer; a second gate structure on the substrate, the second gate structure extending lengthwise in the first direction to have two long sides and two short sides, relative to each other, and including a second gate spacer, wherein a first short side of the second gate structure faces a first short side of the first gate structure; and a gate insulating support disposed between the first short side of the first gate structure and the first short side of the second gate structure and extending lengthwise in a second direction different from the first direction, a length of the gate insulating support in the second direction being greater than a width of each of the first gate structure and the second gate structure in the second direction.

A semiconductor structure (MG) includes a metal gate structure disposed over a semiconductor substrate, a dielectric layer disposed adjacent to the MG, a source/drain (S/D) feature disposed adjacent to the dielectric layer, and a S/D contact disposed over the S/D feature. The S/D contact includes a first metal layer disposed over the S/D feature and a second metal layer disposed on the first metal layer.

In an embodiment, an integrated circuit includes transistors in different active regions, electrically isolated using single diffusion break isolation. The single diffusion break isolation includes a first dummy transistor that has a different threshold voltage than the transistors in either active region for which the single diffusion break is creating isolation. The first dummy transistor may have lower leakage current than transistors in either active region, creating effective isolation between the active regions and consuming relatively small amounts of power due to the lower leakage currents.

A device includes a substrate, and a first semiconductor channel over the substrate. The first semiconductor channel includes a first nanosheet of a first semiconductor material, a second nanosheet of a second semiconductor material in physical contact with a topside surface of the first nanosheet, and a third nanosheet of the second semiconductor material in physical contact with an underside surface of the first nanosheet. The first gate structure is over and laterally surrounding the first semiconductor channel, and in physical contact with the second nanosheet and the third nanosheet.

Semiconductor structures and forming methods are disclosed. One form of a method includes: forming mask spacers on a base; patterning a target layer using the mask spacers as masks, to form discrete initial pattern layers, where the initial pattern layers extend along a lateral direction and grooves are formed between a longitudinal adjacent initial pattern layers; forming boundary defining grooves that penetrate through the initial pattern layers located at boundary positions of the target areas and cutting areas along the lateral direction; forming spacing layers filled into the grooves and the boundary defining grooves; and using the spacing layers located in boundary defining grooves and the spacing layers located in the grooves as stop layers along the lateral and the longitudinal directions respectively, etching the initial pattern layers located in the cutting areas, and using the remaining initial pattern layers located in the target areas as the target pattern layers.

A method of forming a semiconductor structure is provided. The method includes forming a gate structure over an active region of a substrate, forming an epitaxial layer comprising first dopants of a first conductivity type over portions of the active region on opposite sides of the gate structure, the epitaxial layer, applying a cleaning solution comprising ozone and deionized water to the epitaxial layer, thereby forming an oxide layer on the epitaxial layer, forming a patterned photoresist layer over the oxide layer and the gate structure to expose a portion of the oxide layer, forming a contact region second dopants of a second conductivity type opposite the first conductivity type in the portion of the epitaxial layer not covered by the patterned photoresist layer, and forming a contact overlying the contact region.

An embodiment of a method of integration of a non-volatile memory device into a logic MOS flow is described. Generally, the method includes: forming a pad dielectric layer of a MOS device above a first region of a substrate; forming a channel of the memory device from a thin film of semiconducting material overlying a surface above a second region of the substrate, the channel connecting a source and drain of the memory device; forming a patterned dielectric stack overlying the channel above the second region, the patterned dielectric stack comprising a tunnel layer, a charge-trapping layer, and a sacrificial top layer; simultaneously removing the sacrificial top layer from the second region of the substrate, and the pad dielectric layer from the first region of the substrate; and simultaneously forming a gate dielectric layer above the first region of the substrate and a blocking dielectric layer above the charge-trapping layer.

A method of forming a semiconductor device includes etching a substrate to form two first trenches separated by a fin; filling the two first trenches with an isolation layer; and depositing a dielectric layer over the fin and the isolation layer. The method further includes forming a second trench in the dielectric layer over a channel region of the semiconductor device, the second trench exposing the isolation layer. The method further includes etching the isolation layer through the second trench to expose an upper portion of the fin in the channel region of the semiconductor device, and forming a dummy gate in the second trench over the isolation layer and engaging the upper portion of the fin.