A device includes a plurality of fin structures that each protrude vertically upwards out of a substrate and each extend in a first direction in a top view. A gate structure is disposed over the fin structures. The gate structure extends in a second direction in the top view. The second direction is different from the first direction. The fin structures have a fin pitch equal to a sum of: a dimension of one of the fin structures in the second direction and a distance between an adjacent pair of the fin structures in the second direction. An end segment of the gate structure extends beyond an edge of a closest one of the fin structures in the second direction. The end segment has a tapered profile in the top view or is at least 4 times as long as the fin pitch in the second direction.

Disclosed are semiconductor devices and methods of manufacturing the same. The semiconductor device comprises a gate electrode on a substrate, an upper capping pattern on the gate electrode, and a lower capping pattern between the gate electrode and the upper capping pattern. The lower capping pattern comprises a first portion between the gate electrode and the upper capping pattern, and a plurality of second portions extending from the first portion onto corresponding side surfaces of the upper capping pattern. The upper capping pattern covers a topmost surface of each of the second portions.

Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes an isolation structure formed over a semiconductor substrate. A first fin structure and a second fin structure extend from the semiconductor substrate and protrude above the isolation structure. A first gate structure is formed across the first fin structure and a second gate structure is formed across the second fin structure. A gate isolation structure is formed between the first fin structure and the second fin structure and separates the first gate structure from the second gate structure. The gate isolation structure includes a bowl-shaped insulating layer that has a first convex sidewall surface adjacent to the first gate structure and a second convex sidewall surface adjacent to the second gate structure.

A method of controlling gate formation of a semiconductor device includes acquiring a correlation between gate critical dimensions (CDs) and etching recipes for forming gate trenches; measuring a gate CD on a target wafer; determining an etching recipe based on the correction and the measured gate CD; and performing an etching process on the target wafer to form a gate trench with the determined etching recipe.

A semiconductor memory includes a memory cell region that includes multiple memory cells stacked above a semiconductor substrate, first and second dummy regions on opposite sides of the memory cell region, each dummy region including multiple dummy cells stacked above the semiconductor substrate, and a wiring that electrically connects dummy cells of the first and second dummy regions that are at a same level above the semiconductor substrate.

A varactor transistor includes a semiconductor fin having a first conductivity type, a plurality of gate structures separated from each other and surrounding a portion of the semiconductor fin. The plurality of gates structures include a dummy gate structure on an edge of the semiconductor fin, and a first gate structure spaced apart from the dummy gate structure. The dummy gate structure and the gate structure each include a gate insulator layer on a surface portion of the semiconductor fin, a gate on the gate insulator layer, and a spacer on the gate. The varactor transistor also includes a raised source/drain region on the semiconductor fin and between the dummy gate structure and the first gate structure, the raised source/drain region and the gate of the dummy gate structure being electrically connected to a same potential.

A semiconductor device includes a semiconductor structure formed on a substrate, a gate formed on a first side of the semiconductor structure, and a charge collector layer formed on a second side of the semiconductor structure.

Embodiments of the invention are directed to a semiconductor structure that includes a first fin structure having a first sidewall, a first gate structure adjacent a lower portion of the first sidewall, and a first spacer structure over the first gate structure and adjacent an upper portion of first the sidewall. The first spacer structure includes a first spacer structure thickness dimension that extends in a first direction away from the first sidewall. The first gate structure includes a first gate structure thickness dimension that extends in the first direction away from the first sidewall. The first gate structure dimension is about equal to the first spacer structure thickness dimension.

A method of concurrently forming source/drain contacts (CAs) and gate contacts (CBs) and device are provided. Embodiments include forming metal gates (PC) and source/drain (S/D) regions over a substrate; forming an ILD over the PCs and S/D regions; forming a mask over the ILD; concurrently patterning the mask for formation of CAs adjacent a first portion of each PC and CBs over a second portion of the PCs; etching through the mask, forming trenches extending through the ILD down to a nitride capping layer formed over each PC and a trench silicide (TS) contact formed over each S/D region; selectively growing a metal capping layer over the TS contacts formed over the S/D regions; removing the nitride capping layer from the second portion of each PC; and metal filling the trenches, forming the CAs and CBs.

A semiconductor device includes a first active structure on a substrate including a first epitaxial pattern, a second epitaxial pattern and a first channel pattern between the first epitaxial pattern and the second epitaxial pattern, the first channel pattern including at least one channel pattern stacked on the substrate. A first gate structure is disposed on top and bottom surfaces of the first channel pattern. A second active structure on the substrate and includes the second epitaxial pattern, a third epitaxial pattern and a second channel pattern between the second epitaxial pattern and the third epitaxial pattern in the first direction. The second channel pattern includes at least one channel pattern stacked on the substrate. The number of stacked second channel patterns is greater than the number of stacked first channel patterns. A second gate structure is disposed on top and bottom surfaces of the second channel pattern.