Methods for performing a pre-clean process to remove an oxide in semiconductor devices and semiconductor devices formed by the same are disclosed. In an embodiment, a method includes forming a shallow trench isolation region over a semiconductor substrate; forming a gate stack over the shallow trench isolation region; etching the shallow trench isolation region adjacent the gate stack using an anisotropic etching process; and after etching the shallow trench isolation region with the anisotropic etching process, etching the shallow trench isolation region with an isotropic etching process, process gases for the isotropic etching process including hydrogen fluoride (HF) and ammonia (NH.sub.3).

A field effect transistor includes a gate dielectric and a gate electrode overlying an active region and contacting a sidewall of a trench isolation structure. The transistor may be a fringeless transistor in which the gate electrode does not overlie a portion of the trench isolation region. A planar dielectric spacer plate and a conductive gate cap structure may overlie the gate electrode. The conductive gate cap structure may have a z-shaped vertical cross-sectional profile to contact the gate electrode and to provide a segment overlying the planar dielectric spacer plate. Alternatively or additionally, a conductive gate connection structure may be provided to provide electrical connection between two electrodes of adjacent field effect transistors.

Semiconductor device having less defects in a gate insulating film and improved reliability and methods of forming the semiconductor devices are provided. The semiconductor devices may include a gate insulating film on a substrate and a gate electrode structure on the gate insulating film. The gate electrode structure may include a lower conductive film, a silicon oxide film, and an upper conductive film sequentially stacked on the gate insulating film. The lower conductive film may include a barrier metal layer.

Semiconductor devices and methods are provided. A semiconductor device according to the present disclosure includes a first gate-all-around (GAA) transistor having a first plurality of channel members, and a second GAA transistor having a second plurality of channel members. A pitch of the first plurality of channel members is substantially identical to a pitch of the second plurality of channel members. The first plurality of channel members has a first channel member thickness (MT1) and the second plurality of channel members has a second channel member thickness (MT2) greater than the first channel member thickness (MT1).

A semiconductor device according to embodiments includes: a first conductivity-type first semiconductor layer set to a first potential; a second conductivity-type second semiconductor layer stacked on the first semiconductor layer and set to a second potential; an interlayer insulating film disposed on a main surface of the second semiconductor layer; a resistor disposed above the first semiconductor layer while interposing the second semiconductor layer and the interlayer insulating film therebetween; and a terminal electrically connected to the second semiconductor layer.

Disclosed is a thin film transistor, a method for manufacturing the same and a display apparatus comprising the same, wherein the thin film transistor includes a first insulating layer on a substrate, an active layer on the first insulating layer, and a gate electrode spaced apart from the active layer and configured to have at least a portion overlapped with the active layer, wherein the active layer has a single crystal structure of an oxide semiconductor material, and an upper surface of the first insulating layer which contacts the active layer is an oxygen (O) layer made of oxygen (O).

A first dielectric layer is formed over upper and side surfaces of a semiconductor fin structure. A mask layer is formed over a first portion of the first dielectric layer disposed over the upper surface of the fin structure. The mask layer and the first dielectric layer have different material compositions. Second portions of the first dielectric layer disposed on side surfaces of the fin structure are etched. The mask layer protects the first portion of the first dielectric layer from being etched. A second dielectric layer is formed over the mask layer and the side surfaces of the fin structure. An oxidation process is performed to convert the mask layer into a dielectric material having substantially a same material composition as the first or second dielectric layer. The dielectric material and remaining portions of the first or second dielectric layer collectively serve as a gate dielectric of a transistor.

A field effect transistor includes a source region and a drain region formed within and/or above openings in a dielectric capping mask layer overlying a semiconductor substrate and a gate electrode. A source-side silicide portion and a drain-side silicide portion are self-aligned to the source region and to the drain region, respectively.

The present disclosure relates to the technical field of semiconductor manufacturing, and provides a method of manufacturing a semiconductor structure. The method of manufacturing a semiconductor structure includes: providing a substrate; forming a mask layer on the substrate; removing a part of the mask layer on a non-array region; forming a first oxide layer on the non-array region; removing a part of the first oxide layer on a first transistor region, to expose a top surface of the first transistor region; forming an epitaxial layer on the exposed top surface of the first transistor region; removing a part of the first oxide layer on a second transistor region; and forming a second oxide layer on the second transistor region and the epitaxial layer.

A multi-stack semiconductor device includes: a substrate; a multi-stack transistor formed on the substrate and including a nanosheet transistor and a fin field-effect transistor (FinFET) above the nanosheet transistor, wherein the nanosheet transistor includes a plurality nanosheet layers surrounded by a lower gate structure except between the nanosheet layers, the FinFET includes at least one fin structure, of which at least top and side surfaces are surrounded by an upper gate structure, and each of the lower and upper gate structures includes: a gate oxide layer formed on the nanosheet layers and the at least one fin structure; and a gate metal pattern formed on the gate oxide layer. At least one of the lower and upper gate structures includes an extra gate (EG) oxide layer formed between the gate oxide layer and the nanosheet layers and/or between the gate oxide layer and the at least one fin structure.