Semiconductor device structures having low-k features and methods of forming low-k features are described herein. Some examples relate to a surface modification layer, which may protect a low-k feature during subsequent processing. Some examples relate to gate spacers that include a low-k feature. Some examples relate to a low-k contact etch stop layer. Example methods are described for forming such features.

A semiconductor device and a method of forming the same are provided. The method includes forming a sacrificial gate structure over an active region. A first spacer layer is formed along sidewalls and a top surface of the sacrificial gate structure. A first protection layer is formed over the first spacer layer. A second spacer layer is formed over the first protection layer. A third spacer layer is formed over the second spacer layer. The sacrificial gate structure is replaced with a replacement gate structure. The second spacer layer is removed to form an air gap between the first protection layer and the third spacer layer.

The present disclosure relates to a semiconductor device including a substrate and a pair of spacers on the substrate. Each spacer of the pair of spacers includes an upper portion having a first width and a lower portion under the upper portion and having a second width different from the first width. The semiconductor device further includes a gate structure between the pair of spacers. The gate structure has an upper gate length and a lower gate length that is different from the upper gate length.

The on-resistance of each of field effect transistors having different planar sizes is reduced. A semiconductor device includes first and second field effect transistors mounted on a semiconductor substrate and an insulating layer provided on a main surface of the semiconductor substrate. Here, each of the first and second field effect transistors includes a pair of main electrodes which are separated from each other and provided on the main surface of the semiconductor substrate, a cavity part which is provided in the insulating layer between the pair of main electrodes, and a gate electrode which has a head part positioned on the insulating layer and a body part that penetrates the insulating layer from the head part and protrudes toward the cavity part and in which the head part is wider than the body part. Here, the width of the cavity part of the second field effect transistor is different from the width of the cavity part of the first field effect transistor.

Semiconductor structures and methods are provided. A method according to the present disclosure includes providing a workpiece that includes a plurality of active regions including channel regions and source/drain regions, and a plurality of dummy gate stacks intersecting the plurality of active regions at the channel regions, the plurality of dummy gate stacks including a device portion and a terminal end portion. The method further includes depositing a gate spacer layer over the workpiece, anisotropically etching the workpiece to recess the source/drain regions and to form a gate spacer from the gate spacer layer, forming a patterned photoresist layer over the workpiece to expose the device portion and the recessed source/drain regions while the terminal end portion is covered, and after the forming of the patterned photoresist layer, epitaxially forming source/drain features over the recessed source/drain regions.

Semiconductor devices are provided. A semiconductor device includes a substrate. The semiconductor device includes a stack structure on the substrate. The stack structure includes a first insulating material and a second insulating material that is on the first insulating material. The semiconductor device includes a spacer that extends from a sidewall of the first insulating material of the stack structure to a portion of a sidewall of the second insulating material of the stack structure. Moreover, the semiconductor device includes a conductive line that is on the spacer. Methods of forming semiconductor devices are also provided.

A method of forming a semiconductor device that includes forming a trench adjacent to a gate structure to expose a contact surface of one of a source region and a drain region. A sacrificial spacer may be formed on a sidewall of the trench and on a sidewall of the gate structure. A metal contact may then be formed in the trench to at least one of the source region and the drain region. The metal contact has a base width that is less than an upper surface width of the metal contact. The sacrificial spacer may be removed, and a substantially conformal dielectric material layer can be formed on sidewalls of the metal contact and the gate structure. Portions of the conformally dielectric material layer contact one another at a pinch off region to form an air gap between the metal contact and the gate structure.

A method includes forming a first gate stack over a first semiconductor region, depositing a spacer layer on the first gate stack, and depositing a dummy spacer layer on the spacer layer. The dummy spacer layer includes a metal-containing material. An anisotropic etching process is performed on the dummy spacer layer and the spacer layer to form a gate spacer and a dummy sidewall spacer, respectively. The first semiconductor region is etched to form a recess extending into the first semiconductor region. The first semiconductor region is etched using the first gate stack, the gate spacer, and the dummy sidewall spacer as an etching mask. The method further includes epitaxially growing a source/drain region in the recess, and removing the dummy sidewall spacer after the source/drain region is grown.

Various examples of an integrated circuit with a sidewall spacer and a technique for forming an integrated circuit with such a spacer are disclosed herein. In some examples, the method includes receiving a workpiece that includes a substrate and a gate stack disposed upon the substrate. A spacer is formed on a side surface of the gate stack that includes a spacer layer with a low-k dielectric material. A source/drain region is formed in the substrate; and a source/drain contact is formed coupled to the source/drain region such that the spacer layer of the spacer is disposed between the source/drain contact and the gate stack.

Source/drain contacts between transistor gates with abbreviated inner spacers for improved contact area are disclosed. Related methods of fabricating source/drain contacts and abbreviated inner spacers are also disclosed. Inner spacers formed on sidewalls of the gates of adjacent transistors are abbreviated to reduce an amount of the space the inner spacers occupy on the source/drain region, increasing a critical dimension of the source/drain contact. Abbreviated inner spacers extend from a top of the gate over a portion of the sidewalls to provide leakage current protection but do not fully extend to the semiconductor substrate. As a result, the critical dimension of the source/drain contact can extend from a sidewall on a first gate to a sidewall on a second gate. A source/drain contact formed between gates with abbreviated inner spacers has a greater surface area in contact with the source/drain region providing decreased contact resistance.