A device structure is disclosed. The device structure includes a channel region having a first surface facing an underlying substrate and a second surface opposite to the first surface. The device structure includes a gate at least partially surrounding the channel region. The gate includes a gate dielectric and a gate conductor, in which the gate dielectric separates the gate conductor from the channel region. The device structure includes self-aligned source and drain regions (S/D regions) contacting the first and second surfaces, respectively.

A vertical FET includes a channel fin between a bottom source/drain (S/D) region and a top S/D region, a gate upon a sidewall of the channel fin, a top metallization upon the top S/D region, a first contact metallization connected to the gate, a second contact metallization connected to the bottom S/D region, a first vertical liner between a portion of the gate and the first contact metallization, and a second vertical liner between the top metallization and the second contact metallization. The vertical FET may be fabricated by forming a self-aligned block and utilizing the self-aligned block to e.g., prevent gate to gate shorting during replacement gate formation or processing.

Aspects of the present disclosure provide a method for forming a semiconductor structure having separated vertical channel structures. The method can include forming a layer stack on a substrate, the layer stack including alternating metal layers and dielectric layers. The method can further include forming vertically stacked lower and upper vertical channel structures vertically extending through the layer stack, the lower and upper vertical channel structures being separated by a sacrificial layer. The method can further include forming source, drain and gate connections to the lower and upper vertical channel structures, the source, drain and gate connections extending horizontally from the lower and upper vertical channel structures and then vertically to a location above the upper vertical channel structure. The method can further include forming a vertical opening in the layer stack and removing the sacrificial layer through the vertical opening to separate the lower and upper vertical channel structures.

Structures and methods are disclosed in which a layer stack can be formed with a plurality of layers of a metal, where each of the layers of metal can be separated by a layer of a dielectric. An opening in the layer stack can be formed such that a semiconductor layer beneath the plurality of layers of the metal is uncovered. One or more vertical channel structures can be formed within the opening by epitaxial growth. The vertical channel structure can include a vertically oriented transistor. The vertical channel structure can include an interface of a silicide metal with a first metal layer of the plurality of metal layers. The interface can correspond to one of a source or a drain connection of a transistor. The silicide metal can be annealed above a temperature threshold to form a silicide interface between the vertical channel structure and the first metal layer.

A thin film transistor and a non-volatile memory device are provided. The thin film transistor comprises a gate electrode, and a metal oxide channel layer traversing the upper or lower portions of the gate electrode. The metal oxide channel layer has semiconductor properties while having bixbyite crystals. An insulating layer is disposed between the gate electrode and the metal oxide channel layer. Source and drain electrodes are electrically connected to both ends of the metal oxide channel layer, respectively.

A wide band gap semiconductor device includes a semiconductor layer, a trench formed in the semiconductor layer, first, second, and third regions having particular conductivity types and defining sides of the trench, and a first electrode embedded inside an insulating film in the trench. The second region integrally includes a first portion arranged closer to a first surface of the semiconductor layer than to a bottom surface of the trench, and a second portion projecting from the first portion toward a second surface of the semiconductor layer to a depth below a bottom surface of the trench. The second portion of the second region defines a boundary surface with the third region, the boundary region being at an incline with respect to the first surface of the semiconductor layer.

A method of forming a fin field effect transistor (finFET) having fin(s) with reduced dimensional variations, including forming a dummy fin trench within a perimeter of a fin pattern region on a substrate, forming a dummy fin fill in the dummy fin trench, forming a plurality of vertical fins within the perimeter of the fin pattern region, including border fins at the perimeter of the fin pattern region and interior fins located within the perimeter and inside the bounds of the border fins, wherein the border fins are formed from the dummy fin fill, and removing the border fins, wherein the border fins are dummy fins and the interior fins are active vertical fins.

A vertical field effect transistor includes a first epitaxial region in contact with a top surface of a channel fin extending vertically from a bottom source/drain located above a substrate, a second epitaxial region above the first epitaxial region having a horizontal thickness that is larger than a horizontal thickness of the first epitaxial region. The first epitaxial region and the second epitaxial region form a top source/drain region of the semiconductor structure. The first epitaxial region has a first doping concentration and the second epitaxial region has a second doping concentration that is lower than the first doping concentration. A top spacer, adjacent to the first epitaxial region and the second epitaxial region, is in contact with a top surface of a high-k metal gate stack located around the channel fin and in contact with a top surface of a first dielectric layer disposed between adjacent channel fins.

A semiconductor device includes a first MOS structure portion that includes, as its elements, a semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, a first second-semiconductor-layer of a second conductivity type, first semiconductor regions of the first conductivity type, and first gate insulating films, and a second MOS structure portion that includes, as its elements, the substrate, the first semiconductor layer, a second second-semiconductor-layer, second first-semiconductor-regions of the first conductivity type, and second gate insulating films. First and second portions include all of the elements of the first and second MOS structure portions other than the first and second first-semiconductor-regions and the first and second gate insulating films, respectively. A structure of one of the elements of the first portion is not identical to a structure of a corresponding element of the second portion.

Provided is a first vertical field effect transistor in which first source regions and first connection portions via which a first body region is connected to a first source electrode are disposed alternately and cyclically in a first direction in which first trenches extend. In a second direction orthogonal to the first direction, Lxm≤Lxr≤0.20 μm holds true where Lxm denotes a distance between adjacent first trenches and Lxr denotes the inner width of a first trench. The lengths of the first connection portions are in a convergence region in which the on-resistance of the vertical field effect transistor at the time when a voltage having a specification value is applied to first gate conductors to supply current having a specification value does not decrease noticeably even when the lengths of the first connection portions are made much shorter.