A device includes a substrate, a dielectric structure, a gate electrode, and a drain electrode. The dielectric structure is over the substrate. The dielectric structure includes a first portion, a second portion, and a third portion. The first portion has a first equivalent oxide thickness. The second portion is spaced apart from the first portion and has a second equivalent oxide thickness. The third portion laterally surrounds the first and second portions and has a third equivalent oxide thickness greater than the first equivalent oxide thickness of the first portion. The gate electrode is over the dielectric structure and in contact with the first and third portions of the dielectric structure. The drain electrode is over the dielectric structure and in contact with the second and third portions of the dielectric structure.

A parallel structure comprising source/drain and channel layers alternately stacked on a substrate, and gate stacks formed around peripheries of the channel layers. Each of the channel layers, the source/drain layers on upper and lower sides of the channel layer, and the gate stack formed around the channel layer, form a semiconductor device. In each semiconductor device, one of the source/drain layers is in contact with a first electrically-conductive channel disposed on an outer periphery of the active region, the other is in contact with a second electrically-conductive channel on the outer periphery of the active region, and the gate stack is in contact with a third electrically-conductive channel disposed on the outer periphery of the active region. The first electrically-conductive channel is common to the semiconductor devices, the second electrically-conductive channel is common to the semiconductor devices, and the third electronically-conductive channel is common to the semiconductor devices.

The invention provides a semiconductor structure and a manufacturing method making the semiconductor structure. The method includes: providing a substrate; forming semiconductor pillars on the substrate; forming gate electrodes on the middle sidewalls of the semiconductor pillars; and performing dopant implantation to form source and drain regions. Since the gate-all-around (GAA) gates surrounding the semiconductor pillars are formed first, and the source region and the drain region are formed later by doping implantation, the precise position of the doping implantation can be ensured, thereby improving the fabrication accuracy of the semiconductor structure and improving the performance of the semiconductor structure.

The solution provides a device formed in a layer stack that includes a source contact layer and a gate contact layer with a first insulation between the gate contact layer and the source contact layer and a drain contact layer with a second insulation between the gate contact layer and the drain contact layer. The layer stack can include a device region orthogonal to a plane defined by a surface of at least one of the layers of the stack. The device region includes a source and a drain separated by a channel at least partially surrounded by a gate dielectric interposed between the gate contact layer and the channel and a first region that can include a silicide or a germanicide at a first end proximal to the source and a second region that can include the silicide or the germanicide at a second end proximal to the drain.

A semiconductor device is provided. The semiconductor device includes a stack structure disposed on a lower structure; an insulating structure disposed on the stack structure; and a vertical structure extending in a direction perpendicular to an upper surface of the lower structure and having side surfaces opposing the stack structure and the insulating structure. The stack structure includes interlayer insulating layers and gate layers, alternately stacked, and the insulating structure includes a lower insulating layer, an intermediate insulating layer on the lower insulating layer, and an upper insulating layer on the intermediate insulating layer.

A semiconductor device includes: a semiconductor chip; and a field effect transistor formed on the semiconductor chip and including a plurality of unit cells, which include at least one first unit cell including a first on-resistance component and a first feedback capacitance component, and at least one second unit cell including a second on-resistance component forming a parallel component with respect to the first on-resistance component and exceeding the first on-resistance component and a second feedback capacitance component forming a parallel component with respect to the first feedback capacitance component and being less than the first feedback capacitance component.

An image sensor includes: an accumulation unit that accumulates an electric charge generated by a photoelectric conversion unit that photoelectrically converts incident light transmitted through a microlens; and a readout unit that reads out a signal based on a voltage of the accumulation unit, wherein the accumulation unit and the readout unit are included along an optical axis direction of the microlens.

An apparatus comprising a plurality of FET columns located on a substrate. A source/drain layer located around the base of the plurality of FET columns. A dielectric layer located around the source/drain layer, wherein a portion of the dielectric layer that is sandwiched between a first portion of the source/drain layer and a second portion of the source/drain layer. A gate layer, wherein the gate layer has a first portion located on top of the source/drain layer, and wherein the gate layer has a second portion located on top of the portion of the dielectric layer that is sandwiched between a first portion of the source/drain layer and a second portion of the source/drain layer.

A semiconductor device includes an enhancement-mode first p-channel MISFET, an enhancement-mode second p-channel MISFET, a drain conductor electrically and commonly connected to the first p-channel MISFET and the second p-channel MISFET, a first source conductor electrically connected to a source of the first p-channel MISFET, a second source conductor electrically connected to a source of the second p-channel MISFET, and a gate conductor electrically and commonly connected to a gate of the first p-channel MISFET and a gate of the second p-channel MISFET.

A semiconductor device according to an embodiment includes: a first electrode; and a substrate including a first surface in contact with the first electrode and a second surface provided opposite to the first surface, the first surface including a first groove including a first length and a second length shorter than the first length, the first length in a first direction parallel to the first surface, the second length in a second direction parallel to the first surface, the second direction intersecting with the first direction, wherein the substrate includes a semiconductor layer having first conductive type, a first semiconductor region provided between the semiconductor layer and the second surface, the first semiconductor region having second conductive type, a second semiconductor region provided between the first semiconductor region and the second surface, the second semiconductor region having first conductive type higher than an impurity concentration of the semiconductor layer, and a second electrode provided in a first trench, the second electrode being provided opposite to the first semiconductor region via a first insulating film, the first trench reaching the semiconductor layer from the second surface, the first trench extending in the second direction.