An integration manufacturing method of a depletion high voltage NMOS device and a depletion low voltage NMOS device includes: providing a substrate; forming a semiconductor layer on the substrate; forming insulation regions on the semiconductor layer; forming an N-type well in the depletion high voltage NMOS device region; forming a high voltage P-type well in the semiconductor layer, wherein the N-type well and the high voltage P-type well are in contact with each other in a channel direction; forming an oxide layer on the semiconductor layer after the N-type well and the high voltage P-type well formed; forming a low voltage P-type well; and forming an N-type high voltage channel region and an N-type low voltage channel region, such that each of the depletion high voltage NMOS device and the depletion low voltage NMOS device is turned ON when a gate-source voltage thereof is zero voltage.

A semiconductor device can include: a substrate having a first doping type; a first well region located in the substrate and having a second doping type, where the first well region is located at opposite sides of a first region of the substrate; a source region and a drain region located in the first region, where the source region has the second doping type, and the drain region has the second doping type; and a buried layer having the second doping type located in the substrate and below the first region, where the buried layer is incontact with the first well region, where the first region is surrounded by the buried layer and the first well region, and the first doping type is opposite to the second doping type.

An integration manufacturing method of a high voltage device and a low voltage device includes: providing a substrate; forming a semiconductor layer on the substrate; forming insulation regions on the semiconductor layer, for defining a high voltage device region and a low voltage device region; forming a first high voltage well in the high voltage device region; forming a second high voltage well in the semiconductor layer, wherein the first high voltage well and the second high voltage well are in contact with each other in a channel direction; forming an oxide layer on the semiconductor layer, wherein the oxide layer overlays the high voltage device region and the low voltage device region; and forming a first low voltage well in the low voltage device region in the semiconductor layer.

The application provides a method for manufacturing a semiconductor device. The method includes the following operations. A semiconductor substrate is provided, a plurality of separate trenches being formed in the semiconductor substrate. Plasma injection is performed to form a barrier layer between adjacent trenches A respective gate structure is formed in each of the plurality of trenches. A plurality of channel regions are formed in the semiconductor substrate, each of the plurality of trenches corresponding to a respective one of the plurality of channel regions. A source/drain region is formed between each of the plurality of trenches and the barrier layer, the source/drain region being electrically connected to the respective one of the plurality of channel regions, and a conductive type of the barrier layer is opposite to a conductive type of the source/drain region.

A method of manufacturing a semiconductor device is provided. The method of manufacturing a semiconductor device includes an forming a trench in a substrate, forming a gate dielectric layer on the trench, forming a gate layer on the gate dielectric layer, and annealing the gate dielectric layer and the gate layer, wherein, after the first annealing operation, the gate layer includes a molybdenum-tantalum alloy.

Provided is a semiconductor device capable of preventing a malfunction of a high-side gate driver circuit that is caused by a negative voltage surge. A diode is connected between a p-type bulk substrate configuring a semiconductor layer, and a first potential (GND potential), and a signal is transmitted from a control circuit that is formed in an n diffusion region configuring a first semiconductor region through a first level down circuit and a first level up circuit to a high-side gate driver circuit that is formed in an n diffusion region configuring a second semiconductor region. As a result, a malfunction of the high-side gate driver circuit that is caused by a negative voltage surge can be prevented.

A semiconductor device includes a semiconductor substrate having a first conductivity type. First and second wells are located within the substrate, the first well being formed with a dopant of the first conductivity type, e.g. n-type, and the second well formed with a dopant of a second different conductivity type, e.g. p-type. A doped gap region is located between the first and second wells. The doped gap region is formed with a dopant of the second conductivity type, e.g. p-type, at a lower dopant concentration than the dopant concentration in the second well.

In embodiments, a semiconductor device includes a high resistivity substrate, a transistor disposed on the high resistivity substrate, and a deep trench device isolation region disposed in the high resistivity substrate to surround the transistor. Particularly, the high resistivity substrate has a first conductive type, and a deep well region having a second conductive type is disposed in the high resistivity substrate. Further, a first well region having the first conductive type is disposed on the deep well region, and the transistor is disposed on the first well region.

A compact and reliable changeable negative voltage transmission circuit is described. It is very useful for applications need passing changeable negative voltage to selected pins in certain mode. The changeable negative voltage is 0V when enable signal EN is low and −V1 when enable signal EN is high. The circuit includes a control circuit and an output circuit. The control circuit includes a control high power source V.sub.DD and a control low power source V.sub.NEG. The control circuit generates control output signals CON and CON_B to the output circuit to output either 0V if IN is low or −V1 if IN is high when EN is high. Only single type V.sub.T transistor is used in the transmission circuit without any reliability concern, no extra bias voltage is need, which reduces the area and keeps the manufacturing cost low.

The present application relates to a preparation method for a semiconductor device, comprising: sequentially forming an isolating dielectric layer and a doped semiconductor layer of a first conductivity type on a non-primitive cell area of a semiconductor substrate; performing a first conductivity type of well injection by using the semiconductor layer and the isolating dielectric layer as masks, and forming a well area in a primitive cell area; forming an operation structure in the well area, and forming a protection structure in the semiconductor layer; and forming an interlayer dielectric layer on the operation structure and the protection structure, forming a contact hole in the interlayer dielectric layer, forming a metal interconnection layer connected to the contact hole on the interlayer dielectric layer, and connecting the operation structure and the protection structure by means of the metal interconnection layer and the contact hole.