The present invention provides an array substrate and a manufacturing method thereof. The manufacturing method of the array substrate adopts a multi-stage mask to expose and develop, so that a thickness of a remaining photoresist layer in a channel region corresponding to a display region is same as a thickness of a remaining photoresist layer in a channel region corresponding to a GOA region. Therefore, the two channel regions can be completely etched to prevent short-circuiting, and make up for defects of different action efficiency of developers caused by different densities of thin film transistors in the display region and the GOA region.

A semiconductor device includes etch stop films formed on the first gate electrode, the first source region, the first drain region, and the shallow trench isolation regions, respectively. First interlayer insulating films are formed on the etch stop film, respectively. Deep trenches are formed in the substrate between adjacent ones of the first interlayer insulating films to overlap the shallow trench isolation regions. Sidewall insulating films are formed in the deep trenches, respectively. A gap-fill insulating film is formed on the sidewall insulating film. A second interlayer insulating film is formed on the gap-fill insulating film. A top surface of the second interlayer insulating film is substantially planar and a bottom surface of the second interlayer insulating film is undulating.

A semiconductor device includes etch stop films formed on the first gate electrode, the first source region, the first drain region, and the shallow trench isolation regions, respectively. First interlayer insulating films are formed on the etch stop film, respectively. Deep trenches are formed in the substrate between adjacent ones of the first interlayer insulating films to overlap the shallow trench isolation regions. Sidewall insulating films are formed in the deep trenches, respectively. A gap-fill insulating film is formed on the sidewall insulating film. A second interlayer insulating film is formed on the gap-fill insulating film. A top surface of the second interlayer insulating film is substantially planar and a bottom surface of the second interlayer insulating film is undulating.

The present invention discloses a group-III nitride semiconductor device, which comprises a substrate, a buffer layer, a semiconductor stack structure, and a passivation film. The buffer layer is disposed on the substrate. The semiconductor stack structure is disposed on the buffer layer and comprises a gate, a source, and a drain. In addition, a gate insulating layer is disposed between the gate and the semiconductor stack structure for forming a HEMT. The passivation film covers the HEMT and includes a plurality of openings corresponding to the gate, the source, and the drain, respectively. The material of the passivation film is silicon oxynitride.

The present invention discloses a group-III nitride semiconductor device, which comprises a substrate, a buffer layer, a semiconductor stack structure, and a passivation film. The buffer layer is disposed on the substrate. The semiconductor stack structure is disposed on the buffer layer and comprises a gate, a source, and a drain. In addition, a gate insulating layer is disposed between the gate and the semiconductor stack structure for forming a HEMT. The passivation film covers the HEMT and includes a plurality of openings corresponding to the gate, the source, and the drain, respectively. The material of the passivation film is silicon oxynitride.

The present invention relates to an inverter employing a thin film transistor fabricated by adjusting a silicon content and a method for manufacturing the same, and the inverter employing a thin film transistor fabricated by adjusting a silicon content includes a depletion mode transistor including a first gate electrode formed on a substrate, a first insulating layer formed on the first gate electrode, and a first source electrode, a first drain electrode, and a first channel layer formed on the first insulating layer, an enhancement mode transistor including a second gate electrode formed on the substrate, a second insulating layer formed on the second gate electrode, and a second source electrode, a second drain electrode, and a second channel layer formed on the second insulating layer; and a wiring unit electrically connecting the electrodes, and the first channel layer and the second channel layer are formed of amorphous silicon oxide layers having different silicon contents. According to the present invention, an inverter may be configured by adjusting a silicon content of a channel layer with the same electrode layer, only using an oxide thin film transistor of an n channel layer in a CMOS including both a p channel layer and an n channel layer to cause a difference in a threshold voltage.

The present invention relates to an inverter employing a thin film transistor fabricated by adjusting a silicon content and a method for manufacturing the same, and the inverter employing a thin film transistor fabricated by adjusting a silicon content includes a depletion mode transistor including a first gate electrode formed on a substrate, a first insulating layer formed on the first gate electrode, and a first source electrode, a first drain electrode, and a first channel layer formed on the first insulating layer, an enhancement mode transistor including a second gate electrode formed on the substrate, a second insulating layer formed on the second gate electrode, and a second source electrode, a second drain electrode, and a second channel layer formed on the second insulating layer; and a wiring unit electrically connecting the electrodes, and the first channel layer and the second channel layer are formed of amorphous silicon oxide layers having different silicon contents. According to the present invention, an inverter may be configured by adjusting a silicon content of a channel layer with the same electrode layer, only using an oxide thin film transistor of an n channel layer in a CMOS including both a p channel layer and an n channel layer to cause a difference in a threshold voltage.

A semiconductor device includes etch stop films formed on the first gate electrode, the first source region, the first drain region, and the shallow trench isolation regions, respectively. First interlayer insulating films are formed on the etch stop film, respectively. Deep trenches are formed in the substrate between adjacent ones of the first interlayer insulating films to overlap the shallow trench isolation regions. Sidewall insulating films are formed in the deep trenches, respectively. A gap-fill insulating film is formed on the sidewall insulating film. A second interlayer insulating film is formed on the gap-fill insulating film. A top surface of the second interlayer insulating film is substantially planar and a bottom surface of the second interlayer insulating film is undulating.

A semiconductor device includes etch stop films formed on the first gate electrode, the first source region, the first drain region, and the shallow trench isolation regions, respectively. First interlayer insulating films are formed on the etch stop film, respectively. Deep trenches are formed in the substrate between adjacent ones of the first interlayer insulating films to overlap the shallow trench isolation regions. Sidewall insulating films are formed in the deep trenches, respectively. A gap-fill insulating film is formed on the sidewall insulating film. A second interlayer insulating film is formed on the gap-fill insulating film. A top surface of the second interlayer insulating film is substantially planar and a bottom surface of the second interlayer insulating film is undulating.

Provided is a semiconductor device with a reference voltage circuit including an enhancement type transistor having P-type polycrystalline silicon as a first gate electrode, and a depletion type transistor having N-type polycrystalline silicon as a second gate electrode, in which the enhancement type transistor has an impermeable film that is locally provided to cover the first gate electrode via an interlayer insulating film disposed on the first gate electrode, and a nitride film that has an opening portion which is provided larger than the first gate electrode and smaller than the impermeable film, and is provided to cover a periphery of the impermeable film, and the depletion type transistor has a nitride film that is directly provided on an interlayer insulating film disposed on the second gate electrode and covers the depletion type transistor without a gap.