An integrated circuit is provided. The integrated circuit includes a first cell that has a first height and is arranged in a first row which extends in a first direction; a second cell that has a second height and is arranged in a second row which extends in the first direction and is adjacent to the first row, wherein the second cell is adjacent to the first cell in a second direction perpendicular to the first direction; and a power line that extends in the first direction, is arranged on a boundary between the first cell and the second cell, and is configured to supply power to the first cell and the second cell. The first cell overlaps a first width of the power line along the second direction and the second cell overlaps a second width of the power line along the second direction, and the first width and the second width are different from each other.

A standard cell semiconductor device is provided that includes a first and second FET device, each including: (i) a source body and a drain body, each including a common source or drain body portion and a set of source or drain prongs protruding from the common source or drain body portion, (ii) a set of channel layers, each channel layer extending between a pair of source and drain prongs, and (iii) a gate body comprising a common gate body portion and a set of gate prongs protruding from the common gate body portion.

A method includes receiving a design rule deck including a predetermined set of widths and spacings associated with active regions. The method also includes providing a cell library including cells having respective active regions, wherein widths and spacings of the active regions are selected from the predetermined set of the design rule deck. The method includes placing a first cell and a second cell from the cell library in a design layout. The first cell has a cell height in a first direction, and a first active region having a first width in the first direction. The second cell has the cell height, and a second active region having a second width in the first direction. The second width is different from the first width. The method further includes manufacturing a semiconductor device according to the design layout.

A method includes receiving a design rule deck including a predetermined set of widths and spacings associated with active regions. The method also includes providing a cell library including cells having respective active regions, wherein widths and spacings of the active regions are selected from the predetermined set of the design rule deck. The method includes placing a first cell and a second cell from the cell library in a design layout. The first cell has a cell height in a first direction, and a first active region having a first width in the first direction. The second cell has the cell height, and a second active region having a second width in the first direction. The second width is different from the first width. The method further includes manufacturing a semiconductor device according to the design layout.

An integrated circuit layout includes a first and a second standard cells abutting along a boundary line. The boundary line and a first active region of the first standard cell include a distance D1. A first gate line on the first active region protrudes from the first active region by a length L1. The boundary line and a second active region of the second standard cell include a distance D2. A second gate line on the second active region protrudes from the second active region by a length L2. Two first dummy gate lines and two second dummy gate lines are disposed at two sides of the first active region and the second active region and are away from the boundary line by a distance S. The lengths L1 and L2, the distances S, D1 and D2 have the relationships: L1≤D1−S, L2≤D2−S, and D1≠D2.

An integrated circuit includes a first column including a plurality of first cells aligned and placed in a plurality of first rows, each first row having a first width and extending in a first horizontal direction, a second column including a plurality of second cells aligned and placed in a plurality of second rows, each second row having a second width and extending in the first horizontal direction, and an interface column extending in a second horizontal direction perpendicular to the first horizontal direction between the first column and the second column, wherein the interface column includes at least one well tap configured to provide a first supply voltage to a well, and at least one substrate tap configured to provide a second supply voltage to a substrate.

Embodiments of the present application provide an integrated circuit and a layout method thereof. First, a first pitch of a first standard cell having a maximum gate length in multiple standard cells in an integrated circuit is determined. The first pitch is a distance between a central axis of a polysilicon gate in the first standard cell and central axes of virtual polysilicon gates in the first standard cell. Then, a distance between a polysilicon gate and virtual polysilicon gates in each of the standard cells is adjusted by using the first pitch and a gate length of each of the standard cells. After the adjustment, a distance between a central axis of the polysilicon gate in each of the standard cells and central axes of the virtual polysilicon gates in each of the standard cells is the same as the first pitch.

Provided is a semiconductor chip including a nanowire field effect transistor (FET) and having a layout configuration effective for making manufacturing the chip easy. A semiconductor chip includes a first block including a standard cell having a nanowire FET and a second block including a nanowire FET. In the first and second blocks, nanowires extending in an X direction have an arrangement pitch in a Y direction of an integer multiple of a pitch P1. Pads have an arrangement pitch in the X direction of an integer multiple of a pitch P2.

A semiconductor structure is provided. A logic cell with a logic function includes a plurality of first transistors in an active region over a semiconductor substrate, a second transistor in the active region, a third transistor in the active region, and first and second isolation structures on opposite edges of the active region and extending along the first direction. Each first transistor includes a first gate electrode extending along the first direction. The second transistor includes a second gate electrode extending along the first direction. The third transistor includes a third gate electrode extending along the first direction. The first gate electrodes are disposed between the first and second isolation structures. The second gate electrode is disposed between the first gate electrodes and the first isolation structure. The third gate electrode is disposed between the first gate electrodes and the second isolation structure.

Apparatuses including semiconductor layout to mitigate local layout effects arc disclosed. An example apparatus includes a plurality of standard cells each including an active region, an isolation region adjacent the active region, and a first gate structure disposed on the active region and the isolation region. The first gate structure includes a first gate portion disposed on the active region, and a first contact portion disposed on the isolation region. The apparatus further includes a second gate structure disposed on the active region and the isolation region. The second gate structure includes a second gate portion disposed on the active region, and a second contact portion disposed on the isolation region. In the apparatus, a distance between a first contact point and the first gate portion is substantially equal to a distance between a second contact point and the second gate portion.