An integrated circuit includes a first-voltage power rail and a second-voltage power rail in a first connection layer, and includes a first-voltage underlayer power rail and a second-voltage underlayer power rail below the first connection layer. Each of the first-voltage and second-voltage power rails extends in a second direction that is perpendicular to a first direction. Each of the first-voltage and second-voltage underlayer power rails extends in the first direction. The integrated circuit includes a first via-connector connecting the first-voltage power rail with the first-voltage underlayer power rail, and a second via-connector connecting the second-voltage power rail with the second-voltage underlayer power rail.

An integrated circuit (IC) cell including: a first logic gate comprising a first polysilicon structure and a first pin; a second logic gate comprising a second polysilicon structure and a second pin, wherein the second polysilicon structure is spaced apart and adjacent to the first polysilicon structure in a cell row direction; and a source region, common to the first and second logic gates, situated between the first and second polysilicon structures, wherein the first and second pins are on a first metal track directly over the common source region.

A device comprising a semiconductor substrate. The device also comprising a digital block defined on the substrate and having multiple electronic elements. The device also comprises first and second poly layers coupling to the multiple electronic elements, the first and second poly layers extending in parallel through the digital block in a first direction. The device further comprising a third poly layer coupled to the first poly layer and extending through a gap in the second poly layer in a second direction orthogonal to the first direction poly.

A semiconductor die includes a first diffusion region and a plurality of gates extending across the diffusion region. The plurality of gates are substantially parallel to each other. An interconnect layer above the diffusion region and plurality of gates includes a plurality of signal traces extending in a direction substantially perpendicular to the gates. At least two of the plurality of signal traces are located directly above the diffusion region such that at intersections of two gates with two separate signal traces are in the active transistor region, that is the portion of the gate extending over the diffusion region. Gate contacts coupling the two gates to the two separate signal traces are staggered by coupling to different signal traces.

At least one method, apparatus and system disclosed involves an integrated circuit comprising a unidirectional metal layout. A first set of metal features are formed in a vertical configuration in a first metal layer of a memory cell. A second set of metal features are formed in a unidirectional horizontal configuration in a second metal layer of the memory cell. A third set of metal features are formed in the unidirectional horizontal configuration in a second metal layer of a functional cell for providing routing compatibility between the memory cell and the functional cell. The memory cell is placed adjacent to the functional cell for forming an integrated circuit device.

Provided is a semiconductor device in which influence resulting from a cell function change can be reduced. The semiconductor device includes a function cell designed using a basic cell including a first wiring layer provided over a main surface of a semiconductor substrate and having a predetermined pattern and a second wiring layer provided over the first wiring layer and having a predetermined pattern. The function cell corresponds to the basic cell which is modified to have a predetermined function by changing the pattern of the second wiring layer at a design stage. The function cell has a first layout and a second layout which are disposed in juxtaposition in one direction in a plane parallel with the main surface. The function cell is provided with the predetermined function by coupling together wires belonging to the respective second wiring layers of the first layout and the second layout.

A device comprising a semiconductor substrate. The device also comprising a digital block defined on the substrate and having multiple electronic elements. The device also comprises first and second poly layers coupling to the multiple electronic elements, the first and second poly layers extending in parallel through the digital block in a first direction. The device further comprising a third poly layer coupled to the first poly layer and extending through a gap in the second poly layer in a second direction orthogonal to the first direction poly.

Integrated circuits and related logic circuits and structures employing VTFET logic devices. In particular, during middle-of-line (MOL) processing, method steps are employed for forming two-level MOL contact connector structures below first (M1) metallization level wiring formed during subsequent BEOL processing. Using damascene and subtractive metal etch techniques, respective MOL contact connector structures at two levels are formed with a second level above a first level contact. These contact connector structures at two levels below M1 metallization level can provide cross-connections to VTFET devices of logic circuits that enable increased scaling of the logic circuit designs, e.g., especially for multiplexor circuit layouts due to wiring access. The flexible MOL cross-connections made below M1 metallization level provides for much improved M1 and M2 wirability and enable semiconductor circuit layouts that allow for improved cell size reduction without creating significant connection issues at high wiring levels thereby increasing circuit design flexibility.

An integrated circuit device includes a device layer having devices spaced in accordance with a predetermined device pitch, a first metal interconnection layer disposed above the device layer and coupled to the device layer, and a second metal interconnection layer disposed above the first metal interconnection layer and coupled to the first metal interconnection layer through a first via layer. The second metal interconnection layer has metal lines spaced in accordance with a predetermined metal line pitch, and a ratio of the predetermined metal line pitch to predetermined device pitch is less than 1.

An integrated circuit layout structure having dual-height standard cells includes at least a first standard cell including a first cell height and at least a second standard cell including a second cell height. The second cell height is one half of the first cell height. The first standard cell includes one first doped region formed in a middle of the first standard cell and a plurality of second doped regions formed at a top side and a bottom side of the first standard cell. The first doped region includes a first conductivity type and the second doped regions include a second conductivity type complementary to the first conductivity type. And an area of the first doped region is smaller than an area of the total second doped regions.