A semiconductor device includes a substrate including a PMOSFET region and an NMOSFET region. First active patterns are on the PMOSFET region. Second active patterns are on the NMOSFET region. Gate electrodes intersect the first and second active patterns and extend in a first direction. First interconnection lines are disposed on the gate electrodes and extend in the first direction. The gate electrodes are arranged at a first pitch in a second direction intersecting the first direction. The first interconnection lines are arranged at a second pitch in the second direction. The second pitch is smaller than the first pitch.

A first PMOS transistor is defined by a gate electrode extending along a first gate electrode track. A second PMOS transistor is defined by a gate electrode extending along a second gate electrode track. A first NMOS transistor is defined by a gate electrode extending along a third gate electrode track. A second NMOS transistor is defined by a gate electrode extending along a fourth gate electrode track. The gate electrodes of the first PMOS transistor and the first NMOS transistor are electrically connected to a first gate node. The gate electrodes of the second PMOS transistor and the second NMOS transistor are electrically connected to a second gate node. Each of the first PMOS transistor, the first NMOS transistor, the second PMOS transistor, and the second NMOS transistor has a respective diffusion terminal electrically connected to a common output node.

A semiconductor device having a plurality of first wirings (X-direction) which include a first power supply line and a second power supply line, a plurality of third wirings (X-direction) which include a third (fourth) power supply line that is located above the first (second) power supply line and is electrically connected to the first (second) power supply line. The semiconductor device also has a plurality of second wirings (Y-direction) that include a first (second) connection wiring located above the first (second) power supply line and below the third (fourth) power supply line that is electrically connected to the first (second) power supply line and to the third (fourth) power supply line.

A first PMOS transistor is defined by a gate electrode extending along a first gate electrode track. A second PMOS transistor is defined by a gate electrode extending along a second gate electrode track. A first NMOS transistor is defined by a gate electrode extending along the second gate electrode track. A second NMOS transistor is defined by a gate electrode extending along a third gate electrode track. The gate electrodes of the first PMOS transistor and the first NMOS transistor are electrically connected to a first gate node. The gate electrodes of the second PMOS transistor and the second NMOS transistor are electrically connected to a second gate node. Each of the first PMOS transistor, the first NMOS transistor, the second PMOS transistor, and the second NMOS transistor has a respective diffusion terminal electrically connected to a common output node.

The semiconductor structure includes a semiconductor substrate having active regions; field-effect devices disposed on the semiconductor substrate, the field-effect devices including gate stacks with elongated shape oriented in a first direction; a first metal layer disposed over the gate stacks, the first metal layer including first metal lines oriented in a second direction being orthogonal to the first direction; a second metal layer disposed over the first metal layer, the second metal layer including second metal lines oriented in the first direction; and a third metal layer disposed over the second metal layer, the third metal layer including third metal lines oriented in the second direction. The first, second, and third metal lines have a first thickness T.sub.1, a second thickness T.sub.2, and t a third thickness T.sub.3, respectively. The second thickness is greater than the first thickness and the third thickness.

A semiconductor device includes a plurality of standard cells. The plurality of standard cells include a first group of standard cells arranged in a first row extending in a row direction and a second group of standard cells arranged in a second row extending in the row direction. The first group of standard cells and the second group of standard cells are arranged in a column direction. A cell height of the first group of standard cells in the column direction is different from a cell height of the second group of standard cells in the column direction.

A semiconductor device includes a substrate including a PMOSFET region and an NMOSFET region. First active patterns are on the PMOSFET region. Second active patterns are on the NMOSFET region. Gate electrodes intersect the first and second active patterns and extend in a first direction. First interconnection lines are disposed on the gate electrodes and extend in the first direction. The gate electrodes are arranged at a first pitch in a second direction intersecting the first direction. The first interconnection lines are arranged at a second pitch in the second direction. The second pitch is smaller than the first pitch.

The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a semiconductor substrate having a first pair of sidewalls extending in a first direction and a second pair of sidewalls. One or more of the second pair of sidewalls extend past the first pair of sidewalls in a second direction that intersects the first direction as viewed from a top-view of the semiconductor substrate. The first pair of sidewalls and the second pair of sidewalls define one or more trenches within the semiconductor substrate. An interconnecting structure including a conductive material is disposed within the one or more trenches in the semiconductor substrate. The interconnecting structure continuously extends completely through the semiconductor substrate.

The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method may be performed by forming a first device tier including a first semiconductor substrate having a first plurality of devices. A second semiconductor substrate is formed over the first device tier. A first conductive layer is formed within the second semiconductor substrate, and a second conductive layer is formed within the second semiconductor substrate and over the first conductive layer. The first conductive layer and the second conductive layer have different patterns as viewed from a top-view. A second plurality of devices are formed on the second semiconductor substrate. The first and second conductive layers are configured to electrically couple the first plurality of devices and the second plurality of devices.

A semiconductor device includes a plurality of standard cells. The plurality of standard cells include a first group of standard cells arranged in a first row extending in a row direction and a second group of standard cells arranged in a second row extending in the row direction. The first group of standard cells and the second group of standard cells are arranged in a column direction. A cell height of the first group of standard cells in the column direction is different from a cell height of the second group of standard cells in the column direction.