The semiconductor structure includes a semiconductor substrate having active regions; field-effect devices disposed on the semiconductor substrate, the field-effect devices including gate stacks with elongated shape oriented in a first direction; a first metal layer disposed over the gate stacks, the first metal layer including first metal lines oriented in a second direction being orthogonal to the first direction; a second metal layer disposed over the first metal layer, the second metal layer including second metal lines oriented in the first direction; and a third metal layer disposed over the second metal layer, the third metal layer including third metal lines oriented in the second direction. The first, second, and third metal lines have a first thickness T.sub.1, a second thickness T.sub.2, and t a third thickness T.sub.3, respectively. The second thickness is greater than the first thickness and the third thickness.

A MOS device of an IC includes pMOS and nMOS transistors. The MOS device further includes a first M.sub.x layer interconnect extending in a first direction and coupling the pMOS and nMOS transistor drains together, and a second M.sub.x layer interconnect extending in the first direction and coupling the pMOS and nMOS transistor drains together. The first and second M.sub.x layer interconnects are parallel. The MOS device further includes a first M.sub.x+1 layer interconnect extending in a second direction orthogonal to the first direction. The first M.sub.x+1 layer interconnect is coupled to the first M.sub.x layer interconnect and the second M.sub.x layer interconnect. The MOS device further includes a second M.sub.x+1 layer interconnect extending in the second direction. The second M.sub.x+1 layer interconnect is coupled to the first M.sub.x layer interconnect and the second M.sub.x layer interconnect. The second M.sub.x+1 layer interconnect is parallel to the first M.sub.x+1 layer interconnect.

The present disclosure describes an apparatus with a local interconnect structure. The apparatus can include a first transistor, a second transistor, a first interconnect structure, a second interconnect structure, and a third interconnect structure. The local interconnect structure can be coupled to gate terminals of the first and second transistors and routed at a same interconnect level as reference metal lines coupled to ground and a power supply voltage. The first interconnect structure can be coupled to a source/drain terminal of the first transistor and routed above the local interconnect structure. The second interconnect structure can be coupled to a source/drain terminal of the second transistor and routed above the local interconnect structure. The third interconnect structure can be routed above the local interconnect structure and at a same interconnect level as the first and second interconnect structures.

A method for processing a semiconductor wafer uses non-contact electrical measurements indicative of at least one tip-to-tip short or leakage, at least one via-chamfer short or leakage, and at least one corner short or leakage, where such measurements are obtained from cells with respective tip-to-tip short, via-chamfer short, and corner short test areas, using a charged particle-beam inspector with a moving stage and beam deflection to account for motion of the stage.

An IC includes first and second designs of experiments (DOES), each comprised of at least two fill cells. The fill cells contain structures configured to obtain in-line data via non-contact electrical measurements (NCEM). The first DOE contains fill cells configured to enable non-contact (NC) detection of tip-to-side shorts, and the second DOE contains fill cells configured to enable NC detection of corner shorts.

The present disclosure describes an apparatus with a local interconnect structure. The apparatus can include a first transistor, a second transistor, a first interconnect structure, a second interconnect structure, and a third interconnect structure. The local interconnect structure can be coupled to gate terminals of the first and second transistors and routed at a same interconnect level as reference metal lines coupled to ground and a power supply voltage. The first interconnect structure can be coupled to a source/drain terminal of the first transistor and routed above the local interconnect structure. The second interconnect structure can be coupled to a source/drain terminal of the second transistor and routed above the local interconnect structure. The third interconnect structure can be routed above the local interconnect structure and at a same interconnect level as the first and second interconnect structures.

A MOS device of an IC includes pMOS and nMOS transistors. The MOS device further includes a first M.sub.x layer interconnect extending in a first direction and coupling the pMOS and nMOS transistor drains together, and a second M.sub.x layer interconnect extending in the first direction and coupling the pMOS and nMOS transistor drains together. The first and second M.sub.x layer interconnects are parallel. The MOS device further includes a first M.sub.x+1 layer interconnect extending in a second direction orthogonal to the first direction. The first M.sub.x+1 layer interconnect is coupled to the first M.sub.x layer interconnect and the second M.sub.x layer interconnect. The MOS device further includes a second M.sub.x+1 layer interconnect extending in the second direction. The second M.sub.x+1 layer interconnect is coupled to the first M.sub.x layer interconnect and the second M.sub.x layer interconnect. The second M.sub.x+1 layer interconnect is parallel to the first M.sub.x+1 layer interconnect.

An integrated circuit includes a first gate electrode track and a second gate electrode track. The first gate electrode track includes a first gate electrode feature that forms an n-channel transistor as it crosses an n-diffusion region. The first gate electrode track does not cross a p-diffusion region. The second gate electrode track includes a second gate electrode feature that forms a p-channel transistor as it crosses a p-diffusion region. The second gate electrode track does not cross an n-diffusion region. The integrated circuit also includes a linear shaped conductor that crosses both the first and second gate electrode features in a reference direction perpendicular to the first and second gate electrode tracks. The linear shaped conductor provides electrical connection between the first and second gate electrode features.

A method for processing a semiconductor wafer uses non-contact electrical measurements indicative of at least one tip-to-tip short or leakage, at least one tip-to-side short or leakage, and at least one corner short or leakage, where such measurements are obtained from non-contact pads associated with respective tip-to-tip short, tip-to-side short, and corner short test areas.

A method for processing a semiconductor wafer uses non-contact electrical measurements indicative of at least one tip-to-tip short or leakage, at least one tip-to-side short or leakage, and at least one side-to-side short or leakage, where such measurements are obtained from non-contact pads associated with respective tip-to-tip short, tip-to-side short, and side-to-side short test areas.