A semiconductor structure includes an active region, an isolation structure, a first gate structure, and a second gate structure. The active region is disposed over a semiconductor substrate and has a first portion, a second portion, and a third portion. The third portion is between the first portion and the second portion. A shape of the first portion is different from a shape of the third portion, in a top view. The isolation structure is disposed over the semiconductor substrate and surrounds the active region. The first gate structure is disposed between the first portion and the third portion of the active region. The second gate structure is disposed between the second portion and the third portion of the active region.

A semiconductor device for suppressing a variation in characteristics caused by a current flowing at the time of breakdown is disclosed. The first power MOS transistor Q 1 and the column CLM are formed in the first element region FCM defined in the epitaxial layer NEL, and the second power MOS transistor Q 2 is formed in the second element region RCM. The first power MOS transistor Q 1 includes a first trench gate electrode TGE1, and the second power MOS transistor Q 2 includes a second trench gate electrode TGE2. The depth GDP1 of the first trench gate electrode TGE1 is shallower than the depth GDP2 of the second trench gate electrode TGE2.

A non-volatile memory cell includes a selection transistor having an insulated selection gate embedded in a semiconducting substrate region. A semiconducting source region contacts a lower part of the insulated selection gate. A state transistor includes a floating gate having an insulated part embedded in the substrate region above an upper part of the insulated selection gate, a semiconducting drain region, and a control gate insulated from the floating gate and located partially above the floating gate. The source region, the drain region, the substrate region, and the control gate are individually polarizable.

A semiconductor device includes a fin-type pattern on a substrate, a first gate structure being on the fin-type pattern and including first gate spacers and a first gate insulating layer extending along sidewalls of the first gate spacers, a second gate structure being on the fin-type pattern and including second gate spacers and a second gate insulating layer extending along sidewalk of the second gate spacers, a pair of dummy spacers between the first gate structure and the second gate structure, a separation trench being between the pair of dummy spacers and having sidewalls defined by the pair of dummy spacers and the fin-type pattern, a device isolation layer in a portion of the separation trench, and a connection conductive pattern being on the device isolating layer and in the separation trench and contacting the pair of dummy spacers.

A non-volatile memory device includes a substrate. A plurality of shallow trench isolation (STI) lines are disposed on the substrate and extend along a first direction. A memory gate structure is disposed on the substrate between adjacent two of the plurality of STI lines. A trench line is disposed in the substrate and extends along a second direction intersecting the first direction, wherein the trench line also crosses top portions of the plurality of STI lines. A conductive line is disposed in the trench line and used as a selection line to be coupled to the memory gate structure.

A memory device and a manufacturing method of the memory device are provided. The manufacturing method includes steps below. A plurality of stack structures including a tunneling dielectric layer and a floating gate are formed on a substrate. A liner material layer including a nitride liner layer is formed on the substrate. A top surface of the nitride liner layer is lower than a top surface of the floating gate and is higher than a top surface of the tunneling dielectric layer. An isolation material layer covering the liner material layer is formed on the substrate. The isolation material layer is oxidized, and a portion of the isolation material layer is removed to form an isolation structure. An inter-gate dielectric layer covering the stack structures and the isolation structure is formed on the substrate. A control gate covering the inter-gate dielectric layer is formed on the substrate.

A split gate MOSFET is provided. The split gate MOSFET may have a low capacitance between a gate electrode and a source electrode. The trench MOSFET includes a substrate; a gate trench formed on the substrate; a sidewall insulating layer formed on a sidewall of the gate trench; a source electrode surrounded by the sidewall insulating layer; a first upper electrode provided above the source electrode; a first inter-electrode insulating layer formed between the source electrode and the first upper electrode; a second upper electrode formed adjacent to a side of the first upper electrode and surrounding the first upper electrode; and an interlayer insulating layer formed on the first upper electrode and the second upper electrode.

A method for manufacturing a trenched split-gate device, comprising: etching a semiconductor substrate to form a trench (120); depositing an oxide in the trench to form a floating-gate oxide layer in which the floating-gate oxide layer gradually thickens from top to bottom along a side wall of the trench, and a thickness of the floating gate oxide layer at a lower part of the side wall of the trench is the same as that of the floating gate oxide layer at a bottom of the trench; depositing polysilicon into the trench to form a floating-gate polysilicon layer (123); growing an insulation medium on an upper surface of the floating-gate polysilicon layer to form an isolation layer (124); and forming a control gate on the isolation layer in the trench.

A transistor device includes field plate contacts that electrically connect a final metallization layer to field electrodes in underlying trenches, and mesa contacts that electrically connect the final metallization layer to semiconductor mesas confined by the trenches. Each field plate contact is divided into field plate contact segments that are separated from one another. Each mesa contact is divided into mesa contact segments that are separated from one another. In a first area adjacent to an end of the trenches, a first line that runs perpendicular to the trenches intersects a first field plate contact segment of the field plate contacts and a first mesa contact segment of the mesa contacts. In a second area spaced inward from the first area, a second line that runs perpendicular to the trenches intersects a second field plate contact segment of the field plate contacts and a second mesa contact segment of the mesa contacts.

A pair of memory cells that includes first and second spaced apart trenches formed into the upper surface of a semiconductor substrate, and first and second floating gates disposed in the first and second trenches. First and second word line gates disposed over and insulated from a portion of the upper surface that is adjacent to the first and second floating gates respectively. A source region is formed in the substrate laterally between the first and second floating gates. First and second channel regions extend from the source region, under the first and second trenches respectively, along side walls of the first and second trenches respectively, and along portions of the upper surface disposed under the first and second word line gates respectively. The first and second trenches only contain the first and second floating gates and insulation material respectively.