In one embodiment, a semiconductor device is provided with a semiconductor layer made of a nitride semiconductor, a first gate electrode, a first structure body between the first gate electrode and the semiconductor layer, and a first insulating layer between the semiconductor layer and the first structure body. The first structure body has a first intermediate layer made of a conductor to suppress generation of charges at respective interfaces with adjacent layers, a first layer having dielectric property between the first gate electrode and the first intermediate layer, and a second layer having dielectric property between the first gate electrode and the first layer, and has dipoles at an interface between the first layer and the second layer.

A semiconductor device comprises a memory storage component and a transistor in operable communication with the memory storage element. The transistor comprises a source region, a drain region, a gate electrode between the source region and the drain region, a charge trapping material surrounding at least an upper portion of the gate electrode, and an oxide material on sides of the charge trapping material. Related systems and methods are also disclosed.

According to an embodiment, a semiconductor device includes a first electrode, a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a third semiconductor region of the first conductivity type, a gate electrode, and a second electrode. The gate electrode includes a first portion and a second portion. The first portion opposes the third semiconductor region, the second semiconductor region, and a portion of the first semiconductor region in a first direction perpendicular to a second direction from the first electrode toward the first semiconductor region. The second portion is arranged with the first portion in a third direction perpendicular to the first and first directions. The second portion opposes the second semiconductor region in the first direction. A lower end of the second portion is positioned higher than an interface between the first semiconductor region and the second semiconductor region.

A semiconductor device structure includes a hybrid substrate having a semiconductor-on-insulator (SOI) region that includes an active semiconductor layer, a substrate material and a buried insulating material interposed between the active semiconductor layer and the substrate material, and a bulk semiconductor region that includes the substrate material. An insulating structure is positioned in the hybrid substrate, wherein the insulating structure separates the bulk region from the SOI region, and a gate electrode is positioned above the substrate material in the bulk region, wherein the insulating structure is in contact with two opposing sidewalls of the gate electrode.

The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a plurality of upper electrodes separated from a semiconductor substrate by a first dielectric layer. A lower electrode is laterally disposed between the plurality of upper electrodes and between sidewalls of the semiconductor substrate. A second dielectric layer lines opposing sidewalls and a lower surface of the lower electrode. The second dielectric layer laterally separates the lower electrode from the plurality of upper electrodes and from the sidewalls of the semiconductor substrate.

A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, and memory stack structures extending through the alternating stack. Each of the memory stack structures comprises a memory film and a vertical semiconductor channel contacting an inner sidewall of the memory film. The electrically conductive layers include aluminum and silicon and provide low resistance electrically conductive paths as word lines of the three-dimensional memory device. The aluminum-based electrically conductive layers can provide low resistivity, low mechanical stress, and thermal stability for use as high performance word lines.

Various embodiments of the present application are directed to an IC, and associated forming methods. In some embodiments, the IC comprises a memory region and a logic region integrated into a substrate. A memory cell structure is disposed on the memory region. A plurality of logic devices is disposed on the logic region. A first logic device comprises a first logic gate electrode separated from the substrate by a first logic gate dielectric. The first logic gate dielectric is disposed along surfaces of a logic device trench of the substrate, and the first logic gate electrode is disposed on the first logic gate dielectric within the logic device trench. By arranging the first logic gate electrode within the logic device trench, metal layer loss and the resulted sheet resistance and threshold voltage variations and mismatch issues caused by the subsequent planarization process can be improved.

A vertical memory device includes a substrate having a trench structure, gate electrodes on the substrate, the gate electrodes being spaced apart from each other in a first direction substantially vertical to an upper surface of the substrate, a channel including a vertical portion extending through the gate electrodes in the first direction, and a horizontal portion extending in the trench structure in a second direction substantially parallel to the upper surface of the substrate, the horizontal portion being connected the vertical portion, and an epitaxial layer on a first portion of the substrate and connected to the horizontal portion of the channel, the first portion of the substrate being adjacent to ends of the gate electrode in the second direction.

One or more semiconductor devices are provided. The semiconductor device comprises a gate body, a conductive prelayer over the gate body, at least one inhibitor film over the conductive prelayer and a conductive layer over the at least one inhibitor film, where the conductive layer is tapered so as to have a top portion width that is greater than the bottom portion width. One or more methods of forming a semiconductor device are also provided, where an etching process is performed to form a tapered opening such that the tapered conductive layer is formed in the tapered opening.

In one embodiment, a non-volatile memory device includes a vertical state transistor disposed in a semiconductor substrate, where the vertical state transistor is configured to trap charges in a dielectric interface between a semiconductor well and a control gate. A vertical selection transistor is disposed in the semiconductor substrate. The vertical selection transistor is disposed under the state transistor, and configured to select the state transistor.