Semiconductor devices and corresponding methods of manufacture are disclosed. A method includes forming a stack of layers on a substrate. The stack includes a first sacrificial dielectric layer, a first metal layer, a second sacrificial dielectric layer, and a second metal layer vertically stacked on top of one another. The stack is etched to form a vertical opening. The opening is filled with a vertical structure. The vertical structure includes a first sacrificial semiconductor segment, a first semiconductor segment, a second sacrificial semiconductor segment, and a second semiconductor segment. The first and second sacrificial semiconductor segments are removed. Silicide layers are formed in the vertical structure to connect thereto.

Power semiconductor device capable of controlling slope of current and voltage during dynamic switching disclosed. The power semiconductor device may include a semiconductor substrate and a cell array being consisted of a plurality of transistor cells on an active area, wherein each of the plurality of transistor cells may include an emitter region, a body region, a contact region and a gate region, wherein non-uniform threshold voltages may be respectively set in the plurality of transistor cells constituting the cell array, wherein a gate signal may be applied to each of the plurality of transistor cells through an input/output unit, wherein the input/output unit may include a first gate signal path configured for supplying a gate charging current to the gate regions in each of the plurality of transistor cells and a second gate signal path configured for discharging a gate discharging current from the gate region.

A semiconductor device includes: a semiconductor layer; a gate trench formed in the semiconductor layer; an insulating layer formed on the semiconductor layer; a gate electrode buried in the gate trench via the insulating layer; a gate wiring formed on the insulating layer and electrically connected to the gate electrode; and a protection trench formed in the semiconductor layer, wherein the semiconductor layer includes an outer peripheral region including outer edges of the semiconductor layer in a plan view and an inner region surrounded by the outer peripheral region, wherein the gate trench includes an outer peripheral gate trench portion arranged in the outer peripheral region and surrounded by the protection trench in a plan view, and wherein the outer peripheral gate trench portion and the protection trench are formed in a closed annular shape along the outer edges of the semiconductor layer in the outer peripheral region.

A silicon carbide device includes a stripe-shaped trench gate structure extending from a first surface into a silicon carbide body. The gate structure has a gate length along a lateral first direction. A bottom surface and an active first gate sidewall of the gate structure are connected via a first bottom edge of the gate structure. The silicon carbide device further includes at least one source region of a first conductivity type. A shielding region of a second conductivity type is in contact with the first bottom edge of the gate structure across at least 20% of the gate length.

In a silicon carbide semiconductor device and a silicon carbide semiconductor circuit device equipped with the silicon carbide semiconductor device, a gate leak current that flows when negative voltage with respect to the potential of a source electrode is applied to the gate electrode is limited to less than 2×10.sup.−11 A and the gate leak current is limited to less than 3.7×10.sup.−6 A/m.sup.2.

The structure of a semiconductor device with passivation layers on active regions of FET devices and a method of fabricating the semiconductor device are disclosed. The semiconductor device includes a substrate, first and second source/drain (S/D) regions disposed on the substrate, nanostructured channel regions disposed between the first and second S/D regions, a passivation layer, and a nanosheet (NS) structure wrapped around the nanostructured channel regions. Each of the S/D regions have a stack of first and second semiconductor layers arranged in an alternating configuration and an epitaxial region disposed on the stack of first and second semiconductor layers. A first portion of the passivation layer is disposed between the epitaxial region and the stack of first and second semiconductor layers and a second portion of the passivation layer is disposed on sidewalls of the nanostructured channel regions.

A semiconductor device includes a substrate; and a plurality of sub-word line drivers, each of the sub-word line drivers including a plurality of transistors, wherein at least one of the plurality of transistors has a buried gate structure positioned in the substrate.

According to one embodiment, a semiconductor device includes first to third electrodes, a first wiring member, a semiconductor member, and an insulating member. The first wiring member includes a first extending portion. A part of the third electrode is between the first electrode and the first extending portion. An other part of the third electrode is between the first and second electrodes. The semiconductor member is provided between the first and second electrodes and between the first electrode and the first extending portion. The semiconductor member includes first to sixth semiconductor regions. The first semiconductor region includes first and second partial regions. The first partial region is located between the first electrode and the third electrode. The insulating member includes the first insulating region. The first insulating region is provided between the third electrode and the semiconductor member.

A semiconductor device including at least one substrate, a plurality of connection pairs, each equipped with a first connection electrode and a second connection electrode and connected to the terminals of a phase or to the ends of a phase fraction one or more first control electrodes operatively placed between the connection pairs and configured to arrange the pairs in a first electrical configuration and one or more second control electrodes operatively placed between the connection pairs and configured to arrange them in a second electrical configuration.

A cell region of a semiconductor device includes a first and second isolation dummy gates extending along a first direction. The semiconductor device further includes a first gate extending along the first direction and between the first isolation dummy gate and the second isolation dummy gate. The semiconductor device includes a second gate extending along the first direction, the second gate being between the first isolation dummy gate and the second isolation dummy gate relative to a second direction perpendicular to the first direction. The semiconductor device also includes a first active region and a second active region. The first active region extending in the second direction between the first isolation dummy gate and the second isolation dummy gate. The first active region has a first length in the second direction, and the second active region has a second length in the second direction different from the first length.