A semiconductor device includes an insulating substrate, a first semiconductor layer formed of silicon and positioned above the insulating substrate, a second semiconductor layer formed of a metal oxide and positioned above the first semiconductor layer, a first insulating film formed of a silicon nitride and positioned between the first semiconductor layer and the second semiconductor layer, and a block layer positioned between the first semiconductor film and the second semiconductor layer, the block layer hydrogen diffusion of which is lower than that of the first insulating film.

An integrated circuit die may include bottom-gate thin-body transistors. The bottom-gate thin-body transistors may be formed in a thinned-down substrate having a thickness that is defined by shallow trench isolation structures that provide complete well isolation for the transistors. The transistors may include gate terminal contacts formed through the shallow trench isolation structures, bulk terminal contacts that are formed through the thinned substrate and that overlap with the gate contacts, and source-drain terminal contacts with in-situ salicide. Additional metallization layers may be formed over the gate/bulk/source-drain contacts after bonding.

A method is provided for manufacturing a thin film transistor (TFT) backplate that includes a switch TFT and a drive TFT. The method is conducted such that each of the switch TFT and the drive TFT manufactured therewith includes a source electrode/a drain electrode and a gate electrode, and also includes an etching stopper layer, a semiconductor layer, and gate isolation layer that are disposed between the source electrode/the drain electrode and the gate electrode to form a TFT structure. The gate isolation layers of the switch TFT and drive TFT are formed of different materials, such as SiOx and Al.sub.2O.sub.3, or SiOx and SiNx, or Al.sub.2O.sub.3 and a mixture of SiNx and SiOx, such that electrical properties of the switch TFT and the drive TFT are made different.

The present invention provides a semiconductor device relaxing the electric field concentration in a gate insulating film just below a gate electrode, and a production method therefor. The semiconductor device has a third semiconductor layer, a gate insulating film, a gate electrode, and a passivation film. The gate insulating film has a gate electrode contact region being in contact with the gate electrode, and a gate electrode non-contact region not being in contact with the gate electrode. The passivation film has a dielectric constant higher than the dielectric constant of the gate insulating film. A thickness of the gate electrode contact region and a thickness of the gate electrode non-contact region satisfy the following equation 0.8≤t2/t1<1.

According to one embodiment, a semiconductor device includes an insulating substrate including a pixel area and a peripheral circuit area around the pixel area, a first insulating layer which is provided on the insulating substrate and includes at least nitrogen, a second insulating layer at least provided on the first insulating layer of the peripheral circuit area, a first thin-film transistor which is provided above the first insulating layer of the pixel area and includes a first oxide semiconductor layer, and a second thin-film transistor which is provided on the second insulating layer of the peripheral circuit area and includes a second oxide semiconductor layer. The second insulating layer in the pixel area is thinner than that in the peripheral circuit area.

Provided is a transistor with small parasitic capacitance or high frequency characteristics or a semiconductor device including the transistor. An oxide semiconductor film includes a first region in contact with a first conductive film, a second region in contact with a first insulating film, a third region in contact with a third insulating film, a fourth region in contact with a second insulating film, and a fifth region in contact with a second conductive film. The first insulating film is positioned over the first conductive film and the oxide semiconductor film. The second insulating film is positioned over the second conductive film and the oxide semiconductor film. The third insulating film is positioned over the first insulating film, the second insulating film, and the oxide semiconductor film. The third conductive film and the oxide semiconductor film partly overlap with each other with the third insulating film provided therebetween.

The present invention provides a vertical-type thin film transistor (TFT) and methods of fabricating vertical TFTs. The vertical TFT may comprise a source electrode and a drain electrode, the drain electrode and the source electrode being positioned on vertically separated planes. A semiconductor layer may be arranged in between the source electrode and the drain electrode. At least one gate electrode may be embedded in the semiconductor layer. At least one of the source electrode and the drain electrode comprise patterned electrodes. One or all of the gate electrodes, the source electrode and the drain electrode may be patterned electrodes. The patterned electrodes may comprise one or more of fingers or combs, micro perforations, a mesh structure, or a lattice structure. Back side exposed fabrication techniques may be used to fabricate various of the vertical TFT embodiments.

Transistors and method of forming he same include forming a fin on a bottom source/drain region having a channel region and a sacrificial region on the channel region. A gate stack is formed on sidewalls of the channel region. A gate conductor is formed in contact with the gate stack that has a top surface that meets a middle point of sidewalls of the sacrificial region. The sacrificial region is trimmed to create gaps above the gate stack. A top spacer is formed on the gate conductor having airgaps above the gate stack.

Provided is a display device including: a first wiring over an insulating surface; a sidewall over the insulating surface and covering a side surface of the first wiring; an insulating film over the first wiring and the sidewall; and a second wiring over the insulating film, the second wiring intersecting with the first wiring, where an angle of a surface of the sidewall with respect to the insulating surface is smaller than an angle of the side surface of the first wiring with respect to the insulating surface. The angle increases with decreasing distance from the first wiring. An intersection portion of the first wiring and the second wiring is located in a display region of the display device and included in a bent portion of the display device when the display device is bent so that the first wiring is bent.

A method for fabricating an array substrate is disclosed, the array substrate includes a first TFT and a pixel electrode. The method includes: forming a buffer layer (322) on the substrate (321); depositing an active layer film (323, 324) and a transparent electrode layer (326) on the substrate (321) having the buffer layer (322) formed thereon, and forming patterns of an active layer (171), a source/drain electrode (151, 152) and a pixel electrode of the first TFT through a single patterning process. An array substrate and a display device fabricated by the above method are also disclosed. By means of the fabrication method, it significantly reduces the fabrication cycle of the TFT, improves the stability of the TFT, such that threshold voltage of the TFT will not drift severely. Meanwhile, the product yield is improved and the lifetime of the device is extended.