TFT BACKPLATE STRUCTURE AND MANUFACTURE METHOD THEREOF

Abstract

A method is provided for manufacturing a thin film transistor (TFT) backplate that includes a switch TFT and a drive TFT. The method is conducted such that each of the switch TFT and the drive TFT manufactured therewith includes a source electrode/a drain electrode and a gate electrode, and also includes an etching stopper layer, a semiconductor layer, and gate isolation layer that are disposed between the source electrode/the drain electrode and the gate electrode to form a TFT structure. The gate isolation layers of the switch TFT and drive TFT are formed of different materials, such as SiOx and Al.sub.2O.sub.3, or SiOx and SiNx, or Al.sub.2O.sub.3 and a mixture of SiNx and SiOx, such that electrical properties of the switch TFT and the drive TFT are made different.

Claims

1. A manufacture method of a thin-film transistor (TFT) backplate structure, comprising the following steps: Step 1, providing a substrate, depositing a first metal film on the substrate, and patterning the first metal film to form a first gate electrode and a second gate electrode with a distance in between; Step 2, forming a first gate isolation layer on the substrate and the first gate electrode, and forming a second gate isolation layer on the substrate and the second gate electrode; wherein a structure of the first gate isolation layer and a structure of the second gate isolation layer are different; Step 3, depositing an oxide semiconductor film on the first and second gate isolation layers, and patterning the oxide semiconductor film to form a first oxide semiconductor layer and a second oxide semiconductor layer; Step 4, depositing an etching stopper film on the first and second oxide semiconductor layers and the first and second gate isolation layers, and patterning the etching stopper film to form a first etching stopper layer and a second etching stopper layer; Step 5, depositing a second metal film on the first and second etching stopper layers and the first and second gate isolation layers, and patterning the second metal film to form a first source electrode and a first drain electrode, and a second source electrode and a second drain electrode; wherein the first electrode and the first drain electrode are connected to the first oxide semiconductor layer and the second gate electrode, and the second electrode and the second drain electrode are connected to the second oxide semiconductor layer; Step 6, forming a protective layer on the first source electrode and the first drain electrode and the second source electrode and the second drain electrode; and Step 7, forming a pixel electrode on the protective layer; and wherein the pixel electrode is connected to one of the second source electrode and the second drain electrode; and wherein the structure of the first gate isolation layer and the structure of the second gate isolation layer are made different by having the first gate isolation layer and the second gate isolation layer made of first and second materials, respectively, the first and second materials being different from each other, wherein the first and second materials are respectively SiOx and Al.sub.2O.sub.3, or alternatively, the first and second materials are respectively SiOx and SiNx, or alternatively, the first and second materials are respectively Al.sub.2O.sub.3 and a mixture of SiNx and SiOx.

2. The manufacture method of the TFT backplate structure according to claim 1, wherein in Step 2, two masks are employed to respectively form the first gate isolation layer and the second gate isolation layer.

3. The manufacture method of the TFT backplate structure according to claim 1, wherein in Step 2, a half tone mask is employed to form the first gate isolation layer and the second gate isolation layer.

4. The manufacture method of the TFT backplate structure according to claim 1, wherein a thickness of the first gate isolation layer and a thickness of the second gate isolation layer are different.

5. The manufacture method of the TFT backplate structure according to claim 4, wherein the thickness of the first gate isolation layer is 2000 A, and the thickness of the second gate isolation layer is 4000 A.

6. A manufacture method of a thin-film transistor (TFT) backplate structure, comprising the following steps: step 1, providing a substrate, and depositing a first metal film on the substrate, and patterning the first metal film to form a first gate electrode and a second gate electrode with a distance in between; step 2, forming a first gate isolation layer on the on the substrate and the first gate electrode, and forming a second gate isolation layer on the substrate and the second gate electrode; wherein a structure of the first gate isolation layer and a structure of the second gate isolation layer are different; step 3, depositing an oxide semiconductor film on the first and second gate isolation layers, and patterning the oxide semiconductor film to form a first oxide semiconductor layer and a second oxide semiconductor layer; step 4, depositing an etching stopper film on the first and second oxide semiconductor layers and the first and second gate isolation layers, and patterning the etching stopper film to form a first etching stopper layer and a second etching stopper layer; step 5, depositing a second metal film on the first and second etching stopper layers, and the first and second gate isolation layers, and patterning the second metal film to form a first source electrode and a first drain electrode, and a second source electrode and a second drain electrode; wherein the first electrode and the first drain electrode are connected to the first oxide semiconductor layer and one of the first the second gate electrode, and the second electrode and the second drain electrode are connected to the second oxide semiconductor layer; step 6, forming a protective layer on the first source electrode and the first drain electrode, and the second source electrode and the second drain electrode; and step 7, forming a pixel electrode on the protective layer; wherein the pixel electrode is connected to one of the second source electrode and the second drain electrode; wherein the structure of the first gate isolation layer and the structure of the second gate isolation layer are made different by having the first gate isolation layer and the second gate isolation layer made of first and second materials, respectively, the first and second materials being different from each other, wherein the first and second materials are respectively SiOx and Al.sub.2O.sub.3, or alternatively, the first and second materials are respectively SiOx and SiNx, or alternatively, the first and second materials are respectively Al.sub.2O.sub.3 and a mixture of SiNx and SiOx; wherein in Step 2, a half tone mask is employed to form the first gate isolation layer and the second gate isolation layer; and a thickness of the first gate isolation layer and a thickness of the second gate isolation layer are different.

7. The manufacture method of the TFT backplate structure according to claim 6, wherein the thickness of the first gate isolation layer is 2000 A, and the thickness of the second gate isolation layer is 4000 A.

Description

BRIEF DESCRIPTION OF THE DRAWING

[0033] The technical solution, as well as beneficial advantages, of the present invention will be apparent from the following detailed description of an embodiment of the present invention, with reference to the attached drawings.

[0034] In the drawings:

[0035] FIG. 1 is a sectional diagram of a TFT backplate structure according to a first embodiment of the present invention;

[0036] FIG. 2 is a sectional diagram of a TFT backplate structure according to a second embodiment of the present invention;

[0037] FIG. 3 is an electrical property diagram of a switch TFT in the second embodiment of the present invention;

[0038] FIG. 4 is an electrical property diagram of a drive TFT in the second embodiment of the present invention;

[0039] FIG. 5 is a flowchart of a manufacture method of a TFT backplate structure according to the present invention;

[0040] FIG. 6 is a diagram of Step 1 of the manufacture method of the TFT backplate structure according to the present invention;

[0041] FIG. 7 is a diagram of one embodiment of Step 2 in the manufacture method of the TFT backplate structure according to the present invention;

[0042] FIG. 8 is a diagram of another embodiment of Step 2 in the manufacture method of the TFT backplate structure according to the present invention;

[0043] FIG. 9 is a diagram of Step 3 of the manufacture method of the TFT backplate structure according to the present invention;

[0044] FIG. 10 is a diagram of Step 4 of the manufacture method of the TFT backplate structure according to the present invention;

[0045] FIG. 11 is a diagram of Step 5 of the manufacture method of the TFT backplate structure according to the present invention;

[0046] FIG. 12 is a diagram of Step 6 of the manufacture method of the TFT backplate structure according to the present invention; and

[0047] FIG. 13 is a diagram of Step 7 of the manufacture method of the TFT backplate structure according to the present invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

[0048] In order to better understand the characteristics and technical aspect of the invention, reference is made to the following detailed description of the present invention in combination with the diagrams.

[0049] Referring to FIG. 1, a first embodiment of a thin film transistor (TFT) backplate structure according to the present invention is provided. The TFT backplate structure comprises comprising a substrate 1, a first gate electrode 21 and a second gate electrode 22 on the substrate 1 with a distance in between, a first gate isolation layer 31 on the substrate 1 and the first gate electrode 21, a second gate isolation layer 32 on the substrate 1 and the second gate electrode 22, a first oxide semiconductor layer 41 right over the first gate electrode 21 and on the first gate isolation layer 31, a second oxide semiconductor layer 42 right over the second gate electrode 22 and on the second gate isolation layer 32, a first etching stopper layer 51 on the first oxide semiconductor layer 41, a second etching stopper layer 52 on the second oxide semiconductor layer 42, a first source electrode/a first drain electrode 61 on the first gate isolation layer 31 and the first etching stopper layer 51, a second source electrode/a second drain electrode 62 on the second gate isolation layer 32 and the second etching stopper layer 52, a protective layer 7 on the first source electrode/the first drain electrode 61 and the second source electrode/the second drain electrode 62, a pixel electrode 8 on the protective layer 7.

[0050] Both the first gate electrode 21 and the second gate electrode 22 are formed by patterning the same first metal film. Both the first oxide semiconductor layer 41 and the second oxide semiconductor layer 42 are formed by patterning the same oxide semiconductor film. Both the first etching stopper layer 51 and the second etching stopper layer 52 are formed by patterning the same etching stopper film. The first source electrode/the first drain electrode 61 and the second source electrode/the second drain electrode 62 are formed by patterning the same second metal film. The structures of the first gate isolation layer 31 and the second gate isolation layer 32 are different.

[0051] The first source electrode/the first drain electrode 61 are connected to the first oxide semiconductor layer 41 and the second gate electrode 22; the second source electrode/the second drain electrode 62 are connected to the second oxide semiconductor layer 42; the pixel electrode 8 is connected to the second source electrode/the second drain electrode 62.

[0052] The first source electrode/the first drain electrode 61, the first gate electrode 21, and the first etching stopper layer 51, the first semiconductor layer 41, the first gate isolation layer 31 sandwiched in between construct a switch TFT T1; the second source electrode/the second drain electrode 62, the second gate electrode 22, and the second etching stopper layer 52, the second semiconductor layer 42, the second gate isolation layer 32 sandwiched in between construct a drive TFT T2.

[0053] In the first embodiment, the thickness of the first gate isolation layer 31 and the thickness of the second gate isolation layer 32 are the same but the materials thereof are different. The first gate isolation layer 31 and the second gate isolation layer 32 require respective one mask for formation. Specifically, a material of the first gate isolation layer 31 is SiOx and a material of the second gate isolation layer 32 is Al.sub.2O.sub.3; or a material of the first gate isolation layer 31 is SiOx and a material of the second gate isolation layer 32 is SiNx; or a material of the first gate isolation layer 31 is Al.sub.2O.sub.3 and a material of the second gate isolation layer 32 is a mixture of SiNx and SiOx.

[0054] Furthermore, both the first and second oxide semiconductor layers 41, 42 are indium gallium zinc oxide (IGZO) semiconductor layers. The pixel electrode 8 is an indium tin oxide (ITO) pixel electrode.

[0055] Differentiation exists between the switch TFT T1 and the drive TFT T2 to make the electrical properties of the switch TFT T1 and the drive TFT T2 different because the material of the first gate isolation layer 31 and the material of the second gate isolation layer 32 are different; the switch TFT T1 possesses a smaller subthreshold swing S.S for fast charge and discharge; the drive TFT T2 possesses a relatively larger subthreshold swing S.S for more precisely controlling the current and the grey scale. Therefore, the TFT backplate structure can meet the demands of the practical usage to raise the performance of the TFT backplate.

[0056] Referring to FIG. 2, a second embodiment of the TFT backplate structure according to the present invention is provided. A difference of the second embodiment from the first embodiment is that the material of the first gate isolation layer 31 and the material of the second gate isolation layer 32 are the same but the thicknesses thereof are different. The first gate isolation layer 31 and the second gate isolation layer 32 merely require a half tone mask for formation. Specifically, a thickness of the first gate isolation layer 31 is 2000 A, and a thickness of the second gate isolation layer 32 is 4000 A. Other figures are the same as the first embodiment. Repeated description will be omitted here.

[0057] As shown in FIGS. 3 and 4, regarding the aforesaid embodiment, the thickness of the first gate isolation layer 31 constructing the switch TFT T1 is 2000 A, and the subthreshold swing S.S of the switch TFT T1 is 0.1; the thickness of second gate isolation layer 32 constructing the drive TFT T2 is 4000 A, and the subthreshold swing S.S of the drive TFT T2 is larger than 0.4. Obviously, there are obvious differentiation existing between the switch TFT T1 and the drive TFT T2. The electrical properties of the switch TFT T1 and the drive TFT T2 are obviously different; the switch TFT T1 possesses a smaller subthreshold swing S.S for fast charge and discharge; the drive TFT T2 possesses a relatively larger subthreshold swing S.S for more precisely controlling the current and the grey scale. Therefore, the TFT backplate structure can meet the demands of the practical usage to raise the performance of the TFT backplate.

[0058] Referring to FIG. 5, the present invention further provides a manufacture method of a TFT backplate structure, which comprises the following steps:

[0059] Step 1, as shown in FIG. 6, providing a substrate 1, depositing a first metal film on the substrate 1, and patterning the first metal film to form a first gate electrode 21 and a second gate electrode 22 with a distance in between.

[0060] Step 2, forming a first gate isolation layer 31 on the on the substrate 1 and the first gate electrode 21, and forming a second gate isolation layer 32 on the substrate 1 and the second gate electrode 22, such that the first gate isolation layer 31 and the second gate isolation layer 32 have structures that are different.

[0061] Specifically, the implementation of Step 2 is shown in FIG. 7. Two masks are employed to respectively form the first gate isolation layer 31 and the second gate isolation layer 32. A material of the first gate isolation layer 31 and a material of the second gate isolation layer 32 are different. Furthermore, a material of the first gate isolation layer 31 is SiOx and a material of the second gate isolation layer 32 is Al.sub.2O.sub.3; or a material of the first gate isolation layer 31 is SiOx and a material of the second gate isolation layer 32 is SiNx; or a material of the first gate isolation layer 31 is Al.sub.2O.sub.3 and a material of the second gate isolation layer 32 is a mixture of SiNx and SiOx.

[0062] The implementation of Step 2 may alternatively be shown in FIG. 8. A half tone mask is employed to form the first gate isolation layer 31 and the second gate isolation layer 32, and a thickness of the first gate isolation layer 31 and a thickness of the second gate isolation layer 32 are different. Furthermore, a thickness of the first gate isolation layer is 2000 A, and a thickness of the second gate isolation layer is 4000 A.

[0063] Step 3, as shown in FIG. 9, depositing an oxide semiconductor film on the first and second gate isolation layers 31, 32, and patterning the oxide semiconductor film to form a first oxide semiconductor layer 41 and a second oxide semiconductor layer 42.

[0064] Specifically, both the first and second oxide semiconductor layers 41, 42 are IGZO semiconductor layers.

[0065] Step 4, as shown in FIG. 10, depositing an etching stopper film on the first and second oxide semiconductor layers 41, 42 and the first and second gate isolation layers 31, 32, and patterning the etching stopper film to form a first etching stopper layer 51 and a second etching stopper layer 52.

[0066] Step 5, as shown in FIG. 11, depositing a second metal film on the first and second etching stopper layers 51, 52 and the first and second gate isolation layers 31, 32, and patterning the second metal film to form a first source electrode/a first drain electrode 61 and a second source electrode/a second drain electrode 62.

[0067] The first source electrode/the first drain electrode 61 are connected to the first oxide semiconductor layer 41 and the second gate electrode 22, and the second source electrode/the second drain electrode 62 are connected to the second oxide semiconductor layer 42.

[0068] After Step 5 is accomplished, the first etching stopper layer 51, the first semiconductor layer 41, and the first gate isolation layer 31 are disposed between the first source electrode/the first drain electrode 61 and the first gate electrode 21, and all the above elements create a switch TFT T1; the second etching stopper layer 52, the second semiconductor layer 42, and the second gate isolation layer 32 are disposed between the second source electrode/the second drain electrode 62 and the second gate electrode 22, and all the above elements create a drive TFT.

[0069] Step 6, shown in FIG. 12, forming a protective layer 7 on the first source electrode/the first drain electrode 61 and the second source electrode/the second drain electrode 62.

[0070] Step 7, shown in FIG. 13, forming a pixel electrode 8 on the protective layer 7.

[0071] The pixel electrode 8 is connected to the second source electrode/the second drain electrode 62.

[0072] Specifically, the pixel electrode 8 is an ITO pixel electrode.

[0073] Differentiation exists between the switch TFT T1 and the drive TFT T2 to make the electrical properties of the switch TFT T1 and the drive TFT T2 different because the material of the first gate isolation layer 31 and the material of the second gate isolation layer 32 are different according to the method; the switch TFT T1 possesses a smaller subthreshold swing S.S for fast charge and discharge; the drive TFT T2 possesses a relatively larger subthreshold swing S.S for more precisely controlling the current and the grey scale. Therefore, the TFT backplate structure can meet the demands of the practical usage to raise the performance of the TFT backplate.

[0074] In conclusion, according to the TFT backplate structure of the present invention, by arranging the first and second gate isolation layers having different materials or different thicknesses for differentiating the switch TFT and the drive TFT to make that the switch TFT possesses a smaller subthreshold swing for fast charge and discharge, and the drive TFT possesses a larger subthreshold swing for more precisely controlling the current and the grey scale. Accordingly, the switch TFT and the drive TFT have different electrical properties to raise the performance of the TFT backplate. According to the manufacture method of the TFT backplate structure, the first and second gate isolation layers are manufactured with different materials or different thicknesses so that the switch TFT and the drive TFT have different electrical properties to raise the performance of the TFT backplate.

[0075] Above are only specific embodiments of the present invention, the scope of the present invention is not limited to this, and to any persons who are skilled in the art, change or replacement which is easily derived should be covered by the protected scope of the invention. Thus, the protected scope of the invention should go by the subject claims.