A flip chip includes a substrate, an electrode pad layer stacked over the substrate, a passivation layer stacked at both ends of the electrode pad layer, an under bump metallurgy (UBM) layer stacked over the electrode pad layer and the passivation layer, and a bump formed over the UBM layer. The width of an opening on which the passivation layer is not formed over the electrode pad layer is greater than the width of the bump. The flip chip can prevent a crack from being generated in the pad upon ultrasonic bonding.

A semiconductor structure includes a conductive structure over a first passivation layer. The semiconductor structure further includes a second passivation layer over the conductive structure and the first passivation layer. The second passivation layer includes a first oxide film extending along a top surface of the first passivation layer, sidewalls and a top surface of the conductive structure, wherein a top surface of the first oxide film is planar. The second passivation layer further includes a second oxide film over a top surface of the first oxide film and a top surface of the conductive structure, wherein a top surface of the second oxide film is planar. The second passivation layer further includes a third oxide film extending along a top surface of the second oxide film, the sidewalls and the top surface of the conductive structure, wherein a top surface of the third oxide film is curved.

A semiconductor device including an integrated circuit, a protection layer, and a conductive via is provided. The integrated circuit includes at least one conductive pad. The protection layer covers the integrated circuit. The protection layer includes a contact opening, and the conductive pad is exposed by the contact opening of the protection layer. The conductive via is embedded in the contact opening of the protection layer, and the conductive via is electrically connected to the conductive pad through the contact opening. A method of fabricating the above-mentioned semiconductor device and an integrated fan-out package including the above-mentioned semiconductor device are also provided.

A re-distribution layer structure is adapted to be disposed on a substrate having a pad and a protective layer which has a first opening exposing a part of the pad. The re-distribution layer structure includes a first and a second patterned insulating layers and a re-distribution layer. The first patterned insulating layer is disposed on the protective layer and includes at least one protrusion and a second opening corresponding to the first opening. The re-distribution layer is disposed on the first patterned insulating layer and includes a pad portion and a wire portion. The pad portion is located on the first patterned insulating layer. The wire portion includes a body and at least one trench caved in the body. The body extends from the pad portion to the pad exposed by the first and the second openings. The body covers the protrusion, and the at least one protrusion extends into the at least one trench. The second patterned insulating layer covers the wire portion and exposes a part of the pad portion. A manufacturing method of re-distribution layer structure is further provided.

Various embodiments provide a semiconductor device, including a final metal layer having a top side and at least one sidewall; and a passivation layer disposed over at least part of at least one of the top side and the at least one sidewall of the final metal layer; wherein the passivation layer has a substantially uniform thickness.

A chip part includes a substrate that has an upper surface, a lower surface positioned on an opposite side of the upper surface, and a sidewall by which the upper surface and the lower surface are connected together and that has a plurality of concavo-convex portions formed on the sidewall from a side of the upper surface toward a side of the lower surface, a functional element formed at the side of the upper surface of the substrate, a first external electrode and a second external electrode that are arranged at the upper surface of the substrate so as to be electrically connected to the functional element, and a sidewall insulating film with which the sidewall of the substrate is coated so as to fill the plurality of concavo-convex portions formed on the sidewall of the substrate with the sidewall insulating film.

A semiconductor chip includes a semiconductor substrate including a bump region and a non-bump region, a bump on the bump region, and a passivation layer on the bump region and the non-bump region of the semiconductor substrate. No bump is on the non-bump region. A thickness of the passivation layer in the bump region is thicker than a thickness of the passivation layer in the non-bump region. The passivation layer includes a step between the bump region and the non-bump region.

A semiconductor device includes an SiC semiconductor substrate including a diffusion layer, a first electrode provided on the SiC semiconductor substrate, a second electrode provided on the first electrode, and a resin section that is substantially the same size in a plan view as the SiC semiconductor substrate, and that is configured to seal in the second electrode.

A microelectronic device includes a metal layer on a first dielectric layer. An etch stop layer is disposed over the metal layer and on the dielectric layer directly adjacent to the metal layer. The etch stop layer includes a metal oxide, and is less than 10 nanometers thick. A second dielectric layer is disposed over the etch stop layer. The second dielectric layer is removed from an etched region which extends down to the etch stop layer. The etched region extends at least partially over the metal layer. In one version of the microelectronic device, the etch stop layer may extend over the metal layer in the etched region. In another version, the etch stop layer may be removed in the etched region. The microelectronic device is formed by etching the second dielectric layer using a plasma etch process, stopping on the etch stop layer.

The present disclosure discloses a semiconductor device structure with an air gap for reducing capacitive coupling and a method for forming the semiconductor device structure. The semiconductor device structure includes a first conductive pad over a first semiconductor substrate, and a first conductive structure over the first conductive pad. The semiconductor device structure also includes a second conductive structure over the first conductive structure, and a second conductive pad over the second conductive structure. The second conductive pad is electrically connected to the first conductive pad through the first and the second conductive structures. The semiconductor device structure further includes a second semiconductor substrate over the second conductive pad, a first passivation layer between the first and the second semiconductor substrates and covering the first conductive structure, and a second passivation layer between the first passivation layer and the second semiconductor substrate. The first and the second passivation layers surround the second conductive structure, and a first air gap is enclosed by the first and the second passivation layers.