Disclosed is a semiconductor device including a conductive pattern on a substrate, a passivation layer on the substrate and including an opening that partially exposes the conductive pattern, and a pad structure in the opening of the passivation layer and connected to the conductive pattern. The pad structure includes a first metal layer that fills the opening of the passivation layer and has a width greater than that of the opening, and a second metal layer on the first metal layer. The first metal layer has a first thickness at an outer wall of the first metal layer, a second thickness on a top surface of the passivation layer, and a third thickness on a top surface of the conductive pattern. The second thickness is greater than the first thickness, and the third thickness is greater than the second thickness.

According to some embodiments, a semiconductor device includes a semiconductor substrate, a metal portion, a first insulating film, and a second insulating film. The semiconductor substrate has a through-hole extending from a first surface of the semiconductor substrate to a second surface thereof opposite to the first surface. The metal portion is formed in the through-hole. The first insulating film is provided on the second surface of the semiconductor substrate and on a side surface of the through-hole. The second insulating film has a dielectric constant of not more than 6.5 and is provided on a metal portion-side surface of the first insulating film on the side surface of the through-hole of the semiconductor substrate.

Semiconductor apparatus and method for manufacturing semiconductor apparatus are provided. Semiconductor apparatus includes a semiconductor substrate having metal pads, a first passivation layer, a second passivation layer, an under bump metal layer, a stress buffer layer, a copper pillar and a solder structure. First passivation layer is formed on the semiconductor substrate and covers a portion of each metal pad, the first passivation layer has first passivation layer openings to expose a first portion of each metal pad. Second passivation layer is formed on the first passivation layer, the second passivation layer has second passivation layer openings to expose a second portion of each metal pad. Under bump metal layer is formed on the second portion of each metal pad exposed by the second passivation layer opening. Stress buffer layer is formed on the under bump metal layer, and the copper pillar is disposed on the stress buffer layer.

An integrated circuit chip (die) may include a force mitigation system for reducing or mitigating under-pad stresses typically caused by wire bonding. The IC die may include wire bond pads and a force mitigation system formed below each wire bond pad. The force mitigation system may include a shock plate (e.g., metal region), a sealing layer located above the shock plate, and a force mitigation layer including an array of sealed voids between the metal region and the sealing layer. The sealed voids in the force mitigation layer may be defined by forming openings in an oxide dielectric layer and forming a non-conformal sealing layer over the openings to define an array of sealed voids. The force mitigation system may mitigate stresses caused by a wire bond on each wire bond pad, which may reduce or eliminate wire-bond-related damage to semiconductor devices located in the under-pad regions of the die.

A semiconductor device includes a semiconductor body, a stress relieving layer or layer stack disposed over at least part of the semiconductor body, the stress relieving layer or layer stack comprising a plurality of openings which yield a patterned surface topography for the stress relieving layer or layer stack, and a metal layer or layer stack formed on the stress relieving layer or layer stack and occupying the plurality of openings in the stress relieving layer or layer stack. The patterned surface topography of the stress relieving layer or layer stack is transferred to a surface of the metal layer or layer stack facing away from the semiconductor body. The stress relieving layer or layer stack has a different elastic modulus than the metal layer or layer stack over a temperature range.

An integrated circuit chip (die) may include a force mitigation system for reducing or mitigating under-pad stresses typically caused by wire bonding. The IC die may include wire bond pads and a force mitigation system formed below each wire bond pad. The force mitigation system may include a shock plate (e.g., metal region), a sealing layer located above the shock plate, and a force mitigation layer including an array of sealed voids between the metal region and the sealing layer. The sealed voids in the force mitigation layer may be defined by forming openings in an oxide dielectric layer and forming a non-conformal sealing layer over the openings to define an array of sealed voids. The force mitigation system may mitigate stresses caused by a wire bond on each wire bond pad, which may reduce or eliminate wire-bond-related damage to semiconductor devices located in the under-pad regions of the die.

A capacitor that includes a first capacitor layer having a first substrate provided with a first trench structure having a trench, a first electrode, and a second electrode provided in a region of the first trench structure that includes a trench, and a second capacitor layer having a second substrate, a third electrode, and a fourth electrode. Moreover, the first capacitor layer and the second capacitor layer are disposed such that the second electrode and the third electrode oppose each other and are electrically connected.

A resistive element includes: a semiconductor substrate; a lower insulating film deposited on the semiconductor substrate; a resistive layer deposited on the lower insulating film; an interlayer insulating film covering the resistive layer; a pad-forming electrode deposited on the interlayer insulating film, and including a first edge portion connected to one edge portion of the resistive layer and a second edge portion opposite to the first edge portion to be in electrical Schottky contact with the semiconductor substrate; a relay wire having one edge connected to another edge portion of the resistive layer to form an ohmic contact to the semiconductor substrate; and a counter electrode provided under the semiconductor substrate, wherein the resistive element uses a resistance value between the pad-forming electrode and the counter electrode.

A method for manufacturing a semiconductor device includes: providing a semiconductor substrate having first and second sides; forming at least one doping region at the first side; forming a first metallization structure at the first side on and in contact with the at least one doping region; and subsequently forming a second metallization structure at the second side, the second metallization structure forming at least one silicide interface region with the semiconductor substrate and at least one non-silicide interface region with the semiconductor substrate.

A semiconductor device including: a semiconductor element; and a first electrode formed on a first surface of the semiconductor element. The first electrode has a stacked structure including a first electroless Ni plating layer. The first electroless Ni plating layer contains nickel (Ni) and phosphorus (P) as a composition. A phosphorus (P) concentration of the first electroless Ni plating layer is 2.5 wt % to 6 wt % inclusive, and a crystallization rate of Ni.sub.3P in the first electroless Ni plating layer is 0% to 20% inclusive.