An inductive structure may be manufactured with in-situ characterization of dimensions by forming a metal line on a top surface of a semiconductor die, forming a passivation dielectric layer over the metal line, measuring a height profile of a top surface of the passivation dielectric layer as a function of a lateral displacement, forming a magnetic material plate over the passivation dielectric layer, measuring a height profile of a top surface of the magnetic material plate as a function of the lateral displacement, and determining a thickness profile of the magnetic material plate by subtracting the height profile of the top surface of the passivation dielectric layer from the height profile of the top surface of the magnetic material plate. An inductive structure including the magnetic material plate and the metal line is formed.

A display device includes a first planarization film including an opening, a reflective film provided on an inclined surface inside the opening in the first planarization film, an LED chip surrounded by the reflective film and provided inside the opening, and a second planarization film provided on the first planarization film, surrounding the LED chip, and filling the opening, wherein a height from an upper end of the inclined surface of the first planarization film to an interface with air in the second planarization film is 20 μm or less.

A display panel, a manufacturing method thereof, and a display device are disclosed. The display panel includes: a base substrate, provided with a terminal and a terminal protection layer pattern; the terminal protection layer pattern includes a first shielding region and a first opening region, an orthographic projection of the first shielding region on the base substrate and an orthographic projection of the terminal on the base substrate have an overlapping region, the overlapping region is located at an edge of the orthographic projection of the terminal on the base substrate, and an orthographic projection of the first opening region on the base substrate is located in the orthographic projection of the terminal on the base substrate.

A semiconductor package includes a second semiconductor chip disposed on a first semiconductor chip. The first semiconductor chip includes a first semiconductor substrate, a through via, and a lower pad disposed on the through via. The lower pad includes a first segment and a second segment connected thereto. The first segment overlaps the through via. The second segment is disposed on an edge region of the first segment. The second segment has an annular shape. The second semiconductor chip includes a second semiconductor substrate, an upper pad disposed on a bottom surface of the second semiconductor substrate, and a connection terminal disposed between the upper and lower pads. The second segment at least partially surrounds a lateral surface of the upper pad. A level of a top surface of the second segment is higher than that of an uppermost portion of the connection terminal.

There is provided an imaging device including: a first semiconductor substrate having a first region that includes a photoelectric conversion section and a via portion, a second region adjacent to the first region, a connection portion disposed at the second region, and a second semiconductor substrate, wherein the connection portion electrically couples the first semiconductor substrate to the second semiconductor substrate in a stacked configuration, and wherein a width of the connection portion is greater than a width of the via portion.

There is provided a terminal that includes a first conductive layer; a wiring layer on the first conductive layer; a second conductive layer on the wiring layer; and a conductive bonding layer which is in contact with a bottom surface and a side surface of the first conductive layer, a side surface of the wiring layer, a portion of a side surface of the second conductive layer, and a portion of a bottom surface of the second conductive layer, wherein an end portion of the second conductive layer protrudes from an end portion of the first conductive layer and an end portion of the wiring layer, and wherein the conductive bonding layer is in contact with a bottom surface of the end portion of the second conductive layer.

There is provided a terminal that includes a first conductive layer; a wiring layer on the first conductive layer; a second conductive layer on the wiring layer; and a conductive bonding layer which is in contact with a bottom surface and a side surface of the first conductive layer, a side surface of the wiring layer, a portion of a side surface of the second conductive layer, and a portion of a bottom surface of the second conductive layer, wherein an end portion of the second conductive layer protrudes from an end portion of the first conductive layer and an end portion of the wiring layer, and wherein the conductive bonding layer is in contact with a bottom surface of the end portion of the second conductive layer.

Embodiments include semiconductor packages and methods to form the semiconductor packages. A semiconductor package includes a plurality of first dies on a substrate, an interface layer over the first dies, a backside metallization (BSM) layer directly on the interface layer, where the BSM layer includes first, second, and third conductive layer, and a heat spreader over the BSM layer. The first conductive layer includes a titanium material. The second conductive layer includes a nickel-vanadium material. The third conductive layer includes a gold material, a silver material, or a copper material. The copper material may include copper bumps. The semiconductor package may include a plurality of second dies on a package substrate. The substrate may be on the package substrate. The second dies may have top surfaces substantially coplanar to top surface of the first dies. The BSM and interface layers may be respectively over the first and second dies.

Embodiments include semiconductor packages and methods to form the semiconductor packages. A semiconductor package includes a plurality of first dies on a substrate, an interface layer over the first dies, a backside metallization (BSM) layer directly on the interface layer, where the BSM layer includes first, second, and third conductive layer, and a heat spreader over the BSM layer. The first conductive layer includes a titanium material. The second conductive layer includes a nickel-vanadium material. The third conductive layer includes a gold material, a silver material, or a copper material. The copper material may include copper bumps. The semiconductor package may include a plurality of second dies on a package substrate. The substrate may be on the package substrate. The second dies may have top surfaces substantially coplanar to top surface of the first dies. The BSM and interface layers may be respectively over the first and second dies.

In a semiconductor device, a first wiring member is electrically connected to a first main electrode on a first surface of a semiconductor element, and a second wiring member is electrically connected to a second main electrode on a second surface of the semiconductor element. An encapsulating body encapsulates at least a part of each of the first and second wiring members, the semiconductor element and a bonding wire. The semiconductor element has a protective film on the first surface of the semiconductor substrate, and the pad has an exposed surface exposed from an opening of the protective film. The exposed surface includes a connection area to which the bonding wire is connected, and a peripheral area on a periphery of the connection area. The peripheral area has a surface that defines an angle of 90 degrees or less relative to a surface of the connection area.