Patent classifications
H01L2224/05187
Methods of fabricating semiconductor devices having conductive pad structures with multi-barrier films
Methods of fabricating semiconductor devices are provided. The method includes forming an interconnect structure over a substrate. The method also includes forming a passivation layer over the interconnect structure. The method further includes forming an opening in the passivation layer to expose a portion of the interconnect structure. In addition, the method includes sequentially forming a lower barrier film, an upper barrier film, and an aluminum-containing layer in the opening. The lower barrier film and the upper barrier film are made of metal nitride, and the upper barrier film has a nitrogen atomic percentage that is higher than a nitrogen atomic percentage of the lower barrier film and has an amorphous structure.
Methods of fabricating semiconductor devices having conductive pad structures with multi-barrier films
Methods of fabricating semiconductor devices are provided. The method includes forming an interconnect structure over a substrate. The method also includes forming a passivation layer over the interconnect structure. The method further includes forming an opening in the passivation layer to expose a portion of the interconnect structure. In addition, the method includes sequentially forming a lower barrier film, an upper barrier film, and an aluminum-containing layer in the opening. The lower barrier film and the upper barrier film are made of metal nitride, and the upper barrier film has a nitrogen atomic percentage that is higher than a nitrogen atomic percentage of the lower barrier film and has an amorphous structure.
Semiconductor devices having a TSV, a front-side bumping pad, and a back-side bumping pad
Semiconductor devices are provided. The semiconductor devices include a substrate, a first interlayer insulating layer disposed on a front-side of the substrate, a TSV structure passing through the first interlayer insulating layer and the substrate. The TSV structure has a bottom end protruding from a back-side of the substrate, a back-side insulating layer and a back-side passivation layer disposed on the back-side of the substrate, and a bumping pad buried in the back-side insulating layer and the back-side passivation layer and disposed on the bottom end of the TSV structure. The bottom end of the TSV structure protrudes into the back-side bumping pad, and top surfaces of the back-side passivation layer and the back-side bumping pad are coplanar.
Semiconductor devices having a TSV, a front-side bumping pad, and a back-side bumping pad
Semiconductor devices are provided. The semiconductor devices include a substrate, a first interlayer insulating layer disposed on a front-side of the substrate, a TSV structure passing through the first interlayer insulating layer and the substrate. The TSV structure has a bottom end protruding from a back-side of the substrate, a back-side insulating layer and a back-side passivation layer disposed on the back-side of the substrate, and a bumping pad buried in the back-side insulating layer and the back-side passivation layer and disposed on the bottom end of the TSV structure. The bottom end of the TSV structure protrudes into the back-side bumping pad, and top surfaces of the back-side passivation layer and the back-side bumping pad are coplanar.
Method of making a pillar structure having a non-metal sidewall protection structure and integrated circuit including the same
An integrated circuit device includes a semiconductor substrate; and a pad region over the semiconductor substrate. The integrated circuit device further includes an under-bump-metallurgy (UBM) layer over the pad region. The integrated circuit device further includes a conductive pillar on the UBM layer, wherein the conductive pillar has a sidewall surface and a top surface. The integrated circuit device further includes a protection structure over the sidewall surface of the conductive pillar, wherein sidewalls of the UBM layer are substantially free of the protection structure, and the protection structure is a non-metal material.
Method of making a pillar structure having a non-metal sidewall protection structure and integrated circuit including the same
An integrated circuit device includes a semiconductor substrate; and a pad region over the semiconductor substrate. The integrated circuit device further includes an under-bump-metallurgy (UBM) layer over the pad region. The integrated circuit device further includes a conductive pillar on the UBM layer, wherein the conductive pillar has a sidewall surface and a top surface. The integrated circuit device further includes a protection structure over the sidewall surface of the conductive pillar, wherein sidewalls of the UBM layer are substantially free of the protection structure, and the protection structure is a non-metal material.
SEMICONDUCTOR STRUCTURE
A semiconductor structure includes a multi-level interconnect structure, a passivation layer, a barrier layer, and a pad layer. The passivation layer is above the multi-level interconnect structure. The barrier layer lines an inner sidewall of the passivation layer, a top surface of the passivation layer and a top surface of a conductive line of the multi-level interconnect structure. The barrier layer includes a first layer, a second layer, a third layer, and a fourth layer. The first layer is in a nano-crystalline phase. The second layer is above the first layer and in an amorphous phase. The third layer is above the second layer and in a polycrystalline phase. The fourth layer is above the third layer and in a nano-crystalline phase. The pad layer is above the barrier layer.
SEMICONDUCTOR STRUCTURE
A semiconductor structure includes a multi-level interconnect structure, a passivation layer, a barrier layer, and a pad layer. The passivation layer is above the multi-level interconnect structure. The barrier layer lines an inner sidewall of the passivation layer, a top surface of the passivation layer and a top surface of a conductive line of the multi-level interconnect structure. The barrier layer includes a first layer, a second layer, a third layer, and a fourth layer. The first layer is in a nano-crystalline phase. The second layer is above the first layer and in an amorphous phase. The third layer is above the second layer and in a polycrystalline phase. The fourth layer is above the third layer and in a nano-crystalline phase. The pad layer is above the barrier layer.
Non-eutectic bonding
The present invention relates to a method of forming a joint bonding together two solid objects and joints made by the method, where the joint is formed by a layer of a binary system which upon heat treatment forms a porous, coherent and continuous single solid-solution phase extending across a bonding layer of the joint.
Non-eutectic bonding
The present invention relates to a method of forming a joint bonding together two solid objects and joints made by the method, where the joint is formed by a layer of a binary system which upon heat treatment forms a porous, coherent and continuous single solid-solution phase extending across a bonding layer of the joint.