H01L2224/05187

Methods of forming conductive materials on semiconductor devices, and methods of forming electrical interconnects

A method of forming a conductive material on a semiconductor device. The method comprises removing at least a portion of a conductive pad within an aperture in a dielectric material over a substrate. The method further comprises forming a seed material at least within a bottom of the aperture and over the dielectric material, forming a protective material over the seed material within the aperture, and forming a conductive pillar in contact with the seed material through an opening in the protective material over surfaces of the seed material within the aperture. A method of forming an electrical connection between adjacent semiconductor devices, and a semiconductor device, are also described.

Methods of forming conductive materials on semiconductor devices, and methods of forming electrical interconnects

A method of forming a conductive material on a semiconductor device. The method comprises removing at least a portion of a conductive pad within an aperture in a dielectric material over a substrate. The method further comprises forming a seed material at least within a bottom of the aperture and over the dielectric material, forming a protective material over the seed material within the aperture, and forming a conductive pillar in contact with the seed material through an opening in the protective material over surfaces of the seed material within the aperture. A method of forming an electrical connection between adjacent semiconductor devices, and a semiconductor device, are also described.

Bond pad structure

A bond pad structure includes a first oxide layer that overlies a substrate. A plurality of adhesion structures are formed over the first oxide layer. A second oxide layer is formed over the plurality of adhesion structures and the first oxide layer. Each one of a plurality of contact openings formed within a surface region of the second oxide layer includes one or more sides and is aligned over at least a portion of a top surface of a corresponding one of the plurality of adhesion structures. A barrier layer is formed within the surface region that is over the second oxide layer and within the plurality of contact openings and over the at least a portion of the top surface of the corresponding ones of the plurality of adhesion structures. A metal layer is formed over the barrier layer.

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

A semiconductor structure includes a multi-level interconnect structure, a passivation layer, a barrier layer, and a pad layer. The passivation layer is above the multi-level interconnect structure. The barrier layer lines an inner sidewall of the passivation layer, a top surface of the passivation layer and a top surface of a conductive line of the multi-level interconnect structure. The barrier layer includes a first layer, a second layer, a third layer, and a fourth layer. The first layer is in a nano-crystalline phase. The second layer is above the first layer and in an amorphous phase. The third layer is above the second layer and in a polycrystalline phase. The fourth layer is above the third layer and in a nano-crystalline phase. The pad layer is above the barrier layer.

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

A semiconductor structure includes a multi-level interconnect structure, a passivation layer, a barrier layer, and a pad layer. The passivation layer is above the multi-level interconnect structure. The barrier layer lines an inner sidewall of the passivation layer, a top surface of the passivation layer and a top surface of a conductive line of the multi-level interconnect structure. The barrier layer includes a first layer, a second layer, a third layer, and a fourth layer. The first layer is in a nano-crystalline phase. The second layer is above the first layer and in an amorphous phase. The third layer is above the second layer and in a polycrystalline phase. The fourth layer is above the third layer and in a nano-crystalline phase. The pad layer is above the barrier layer.

BONDED BODY, CIRCUIT BOARD, AND SEMICONDUCTOR DEVICE

A bonded body according to an embodiment includes a substrate, a metal member, and a bonding layer. The bonding layer is provided between the substrate and the metal member. The bonding layer includes a first particle including carbon, a first region including a metal, and a second region including titanium. The second region is provided between the first particle and the first region. A concentration of titanium in the second region is greater than a concentration of titanium in the first region.

Semiconductor device

A semiconductor device according to an embodiment includes a first substrate including a first insulating layer, a first conductive layer provided in the first insulating layer, a first metal layer provided in the first insulating layer, and a second metal layer provided between the first metal layer and the first conductive layer, a linear expansion coefficient of the second metal layer being higher than that of the first metal layer; and a second substrate including a second insulating layer, and a third metal layer provided in the second insulating layer, in contact with the first metal layer. The second substrate contacts with the first substrate.

Semiconductor device

A semiconductor device according to an embodiment includes a first substrate including a first insulating layer, a first conductive layer provided in the first insulating layer, a first metal layer provided in the first insulating layer, and a second metal layer provided between the first metal layer and the first conductive layer, a linear expansion coefficient of the second metal layer being higher than that of the first metal layer; and a second substrate including a second insulating layer, and a third metal layer provided in the second insulating layer, in contact with the first metal layer. The second substrate contacts with the first substrate.

SEMICONDUCTOR DEVICES HAVING CONDUCTIVE PAD STRUCTURES WITH MULTI-BARRIER FILMS

Semiconductor devices are provided. The semiconductor device includes a substrate, an interconnect structure, and a conductive pad structure. The interconnect structure is over the substrate and includes a top metal layer. The conductive pad structure is over the interconnect structure and includes a lower barrier film, an upper barrier film, and an aluminum-containing layer. The lower barrier film is on the top metal layer. The upper barrier film is on the lower barrier film and has an amorphous structure. The aluminum-containing layer is on the upper barrier film. The lower barrier film and the upper barrier film are made of a same material, and a nitrogen atomic percentage of the upper barrier film is higher than a nitrogen atomic percentage of the lower barrier film.

SEMICONDUCTOR DEVICES HAVING CONDUCTIVE PAD STRUCTURES WITH MULTI-BARRIER FILMS

Semiconductor devices are provided. The semiconductor device includes a substrate, an interconnect structure, and a conductive pad structure. The interconnect structure is over the substrate and includes a top metal layer. The conductive pad structure is over the interconnect structure and includes a lower barrier film, an upper barrier film, and an aluminum-containing layer. The lower barrier film is on the top metal layer. The upper barrier film is on the lower barrier film and has an amorphous structure. The aluminum-containing layer is on the upper barrier film. The lower barrier film and the upper barrier film are made of a same material, and a nitrogen atomic percentage of the upper barrier film is higher than a nitrogen atomic percentage of the lower barrier film.