A three-dimensional (3D) integrated circuit (IC) is provided. In some embodiments, the 3D IC comprises a first IC die comprising a first substrate, a first interconnect structure disposed over the first substrate, and a first through substrate via(TSV) disposed through the first substrate. The 3D IC further comprises a second IC die comprising a second substrate, a second interconnect structure disposed over the second substrate, and a second TSV disposed through the second substrate. The 3D IC further comprises a bonding structure arranged between back sides of the first IC die and the second IC die opposite to corresponding interconnect structures and bonding the first IC die and the second IC die. The bonding structure comprises conductive features disposed between and electrically connecting the first TSV and the second TSV.

A semiconductor die may be coupled to a printed circuit board using a solder ball. The semiconductor die comprises a redistribution layer formed above a semiconductor chip, a polymer layer formed on the redistribution layer, and an Under Bump Metallurgy (UBM) layer formed on the polymer layer. The polymer layer comprises a plurality of vias, which electrically couple the UBM layer to the redistribution layer. The entire UBM layer may be deposited with a continuously flat upper surface for coupling to the solder ball. The plurality of vias may be positioned such that they are centered on a point that is not central to the UBM layer.

A dielectric film is disposed on a semiconductor substrate, and a conductor including a bent section is arranged between the semiconductor substrate and the dielectric film. A pad is disposed on the dielectric film. The pad is covered with a protective film. The protective film has an opening through which an upper surface of the pad is exposed. The bent section in the conductor and the pad overlap each other as seen in plan view, and an inside corner and an outside corner in the bent section are chamfered.

A method for manufacturing three-dimensional (3D) integrated circuit (IC) is provided. In some embodiments, a second IC die is formed and bonded to a first IC die by a first bonding structure. A third IC die is formed and bonded to the second IC die by a second bonding structure. The second bonding structure is formed between back sides of the second IC die and the third IC die opposite to corresponding interconnect structures and comprises a first TSV (through substrate via) disposed through a second substrate of the second IC die and a second TSV disposed through a third substrate of the third IC die. In some further embodiments, the second bonding structure is formed by forming conductive features with oppositely titled sidewalls disposed between the first TSV and the second TSV.

The present application discloses a semiconductor device with slanted conductive layers and a method for fabricating the semiconductor device with the slanted conductive layers. The semiconductor device includes a substrate, a first insulating layer positioned above the substrate, first slanted conductive layers positioned in the first insulating layer, and a top conductive layer positioned covering the first slanted conductive layers.

Provided is a package structure including a bottom die, a top die, an insulating layer, a circuit substrate, a dam structure, and an underfill. The top die is bonded on a front side of the bottom die. The insulating layer is disposed on the front side of the bottom die to laterally encapsulate a sidewall of the top die. The circuit substrate is bonded on a back side of the bottom die through a plurality of connectors. The dam structure is disposed between the circuit substrate and the back side of the bottom die, and connected to the back side of the bottom die. The underfill laterally encapsulates the connectors and the dam structure. The dam structure is electrically isolated from the circuit substrate by the underfill. A method of forming the package structure is also provided.

A semiconductor structure includes a semiconductor die having an active surface, a passivation layer covering the active surface of the semiconductor die, and a post-passivation interconnect (PPI) layer disposed over the passivation layer. The PPI layer includes a ball pad having a first diameter. A polymer layer covers a perimeter of the ball pad. An under-bump-metallurgy (UBM) layer is disposed on the ball pad. The UBM layer has a second diameter that is greater than the first diameter of the ball pad. A solder ball is mounted on the UBM layer.

A semiconductor chip includes a semiconductor substrate having a first surface and a second surface opposite to the first surface. An active layer is disposed in a portion of the semiconductor substrate adjacent to the first surface. A through electrode extends in the semiconductor substrate in a vertical direction. The through electrode has a lower surface connected to the active layer and an upper surface positioned at a level lower than a level of the second surface of the semiconductor substrate. A passivation layer is disposed on the second surface of the semiconductor substrate. A bonding pad is arranged on a portion of the passivation layer and the upper surface of the through electrode. The bonding pad has a cross-section with a “T” shape in the vertical direction. The bonding pad is connected to the through electrode.

An integrated circuit structure includes a substrate with a circuit region thereon and a copper interconnect structure disposed on the substrate. The copper interconnect structure includes an uppermost copper layer covered by a dielectric layer. An aluminum pad layer is provided on the dielectric layer. A metal layer is provided on the circuit region and is located between the uppermost copper layer and the aluminum pad layer.

A device structure may include an interconnect-level dielectric material layer located over a substrate, a first metal interconnect structure embedded in the interconnect-level dielectric material layer and including a first metallic barrier liner and a first metallic fill material portion, and an overlying dielectric material layer. An opening in the overlying dielectric material layer may be formed entirely within an area of the first metallic barrier layer and outside the area of the first metallic fill material portion to reduce plasma damage. A second metal interconnect structure contacting a top surface of the first metallic barrier liner may be formed in the opening. An entirety of a top surface the first metallic fill material portion contacts a bottom surface of the overlying dielectric material layer.