A semiconductor device includes a semiconductor substrate, a power transistor formed in the semiconductor substrate, the power transistor including an active area in which one or more power transistor cells are formed, a first metal pad formed above the semiconductor substrate and covering substantially all of the active area of the power transistor, the first metal pad being electrically connected to a source or emitter region in the active area of the power transistor, the first metal pad including an interior region laterally surrounded by a peripheral region, the peripheral region being thicker than the interior region, and a first interconnect plate or a semiconductor die attached to the interior region of the first metal pad by a die attach material. Corresponding methods of manufacture are also described.

Disclosed embodiments include a semiconductor chip including a semiconductor substrate having a top surface with a top connection pad disposed therein, and a protection insulation layer comprising an opening therein, the protection insulation layer not covering at least a portion of the top connection pad, on the semiconductor substrate. The protection insulation layer may include: a bottom protection insulation layer, a cover insulation layer comprising a side cover part that covers at least a portion of a side surface of the bottom protection insulation layer and a top cover part disposed apart from the side cover part to cover at least a portion of a top surface of the bottom protection insulation layer. The protection insulation layer may further include a top protection insulation layer on the top cover part.

A device includes a first side interconnect structure over a first side of a substrate, wherein active circuits are in the substrate and adjacent to the first side of the substrate, a dielectric layer over a second side of the substrate, a pad embedded in the dielectric layer, the pad comprising an upper portion and a bottom portion formed of two different materials and a passivation layer over the dielectric layer.

Semiconductor dies having interconnect structures formed thereon, and associated systems and methods, are disclosed herein. In one embodiment, an interconnect structure includes a conductive material electrically coupled to an electrically conductive contact of a semiconductor die. The conductive material includes a first portion vertically aligned with the conductive contact, and a second portion that extends laterally away from the conductive contact. A solder material is disposed on the second portion of the interconnect structure such that the solder material is at least partially laterally offset from the conductive contact of the semiconductor die. In some embodiments, an interconnect structure can further include a containment layer that prevents wicking or other undesirable movement of the solder material during a reflow process.

The present technology is directed to manufacturing collars for under-bump metal (UBM) structures for die-to-die and/or package-to-package interconnects and associated systems. A semiconductor die includes a semiconductor material having solid-state components and an interconnect extending at least partially through the semiconductor material. An under-bump metal (UBM) structure is formed over the semiconductor material and is electrically coupled to corresponding interconnects. A collar surrounds at least a portion of the side surface of the UBM structure, and a solder material is disposed over the top surface of the UBM structure.

A device includes a first side interconnect structure over a first side of a substrate, wherein active circuits are in the substrate and adjacent to the first side of the substrate, a dielectric layer over a second side of the substrate, a pad embedded in the dielectric layer, the pad comprising an upper portion and a bottom portion formed of two different materials and a passivation layer over the dielectric layer.

A semiconductor device includes a semiconductor substrate, a power transistor formed in the semiconductor substrate, the power transistor including an active area in which one or more power transistor cells are formed, a first metal pad formed above the semiconductor substrate and covering substantially all of the active area of the power transistor, the first metal pad being electrically connected to a source or emitter region in the active area of the power transistor, the first metal pad including an interior region laterally surrounded by a peripheral region, the peripheral region being thicker than the interior region, and a first interconnect plate or a semiconductor die attached to the interior region of the first metal pad by a die attach material. Corresponding methods of manufacture are also described.

A method of forming a conductive material on a semiconductor device. The method comprises removing at least a portion of a conductive pad within an aperture in a dielectric material over a substrate. The method further comprises forming a seed material at least within a bottom of the aperture and over the dielectric material, forming a protective material over the seed material within the aperture, and forming a conductive pillar in contact with the seed material through an opening in the protective material over surfaces of the seed material within the aperture. A method of forming an electrical connection between adjacent semiconductor devices, and a semiconductor device, are also described.

This disclosure provides a display substrate, a production method thereof, and a display apparatus. The display substrate comprises: a display area; and a pad area outside the display area. The pad area comprises at least one pad. The pad comprises: a metal layer, which comprises a first metal sublayer and a second metal sublayer laminated on the first metal sublayer, wherein a corrosion resistance of the second metal sublayer is stronger than that of the first metal sublayer; and a conductive material layer, which covers a side surface of the metal layer.

Semiconductor dies having interconnect structures formed thereon, and associated systems and methods, are disclosed herein. In one embodiment, an interconnect structure includes a conductive material electrically coupled to an electrically conductive contact of a semiconductor die. The conductive material includes a first portion vertically aligned with the conductive contact, and a second portion that extends laterally away from the conductive contact. A solder material is disposed on the second portion of the interconnect structure such that the solder material is at least partially laterally offset from the conductive contact of the semiconductor die. In some embodiments, an interconnect structure can further include a containment layer that prevents wicking or other undesirable movement of the solder material during a reflow process.