The present technology is directed to manufacturing collars for under-bump metal (UBM) structures for die-to-die and/or package-to-package interconnects and associated systems. A semiconductor die includes a semiconductor material having solid-state components and an interconnect extending at least partially through the semiconductor material. An under-bump metal (UBM) structure is formed over the semiconductor material and is electrically coupled to corresponding interconnects. A collar surrounds at least a portion of the side surface of the UBM structure, and a solder material is disposed over the top surface of the UBM structure.

The present disclosure relates to an integrated circuit having a bond pad with a relatively flat surface topography that mitigates damage to underlying layers. In some embodiments, the integrated circuit has a plurality of metal interconnect layers within a dielectric structure over a substrate. A passivation structure is arranged over the dielectric structure. The passivation structure has a recess with sidewalls connecting a horizontal surface of the passivation structure to an upper surface of the passivation structure. A bond pad is arranged within the recess and has a lower surface overlying the horizontal surface. One or more protrusions extend outward from the lower surface through openings in the passivation structure to contact one of the metal interconnect layers. Arranging the bond pad within the recess and over the passivation structure mitigates stress to underlying layers during bonding without negatively impacting an efficiency of an image sensing element within the substrate.

To prevent a tin alloy from coming into contact with a copper wiring layer when a tin alloy bump layer is reflowed. According to an aspect of the present invention, a method of manufacturing a substrate having a bump at a resist opening is provided. The method of manufacturing a substrate includes a step of forming a copper wiring layer on the substrate by plating at a first temperature, a step of forming a barrier layer on the copper wiring layer by plating at a second temperature that is approximately equal to the first temperature, and a step of forming a tin alloy bump layer on the barrier layer by plating.

A semiconductor device is provided that can minimize the occurrence of poor joining between a copper electrode and a copper wire. The semiconductor device includes a semiconductor substrate; a copper electrode layer formed on the semiconductor substrate; a metallic thin-film layer formed on the copper electrode layer for preventing oxidation of the copper electrode layer, the metallic thin-film layer having an opening through which the copper electrode layer is exposed, the opening being located on an inner side relative to an outer periphery of the metallic thin-film layer; and an interconnection member containing copper as a main component, the interconnection member including a joining region covering the opening, the interconnection member being joined to the metallic thin-film layer and joined to the copper electrode layer in the opening.

A semiconductor device includes a passivation layer over a dielectric layer, a via through the passivation layer and the dielectric layer, an interconnection metallization arranged over said at least one via; said passivation layer underlying peripheral portions of said interconnection metallization, and an outer surface coating that coats said interconnection metallization. The coating preferably includes at least one of a nickel or nickel alloy layer and a noble metal layer. The passivation layer is separated from the peripheral portion of the interconnection metallization by a diffusion barrier layer, preferably a titanium or a titanium alloy barrier. The device includes a dielectric layer arranged between the passivation layer and the diffusion barrier layer; and a hollow recess area between the passivation layer and the end portion of the barrier layer and between the passivation layer and the foot of the outer surface coating.

A semiconductor device includes a passivation layer, an interconnection metallization 37 having a peripheral portion over the passivation layer, and an outer surface coating 37 on the interconnection metallization. A diffusion barrier layer comprises an inner planar portion directly on the surface of the passivation layer and a peripheral portion extending along a plane at a vertical height higher than the surface of the passivation layer, so that the peripheral portion forms with the inner portion a step in the barrier layer. The outer surface coating, has a vertical wall with a foot adjacent to the peripheral portion and positioned at the vertical height over the surface of the passivation layer to form a hollow recess area between the surface of the passivation layer and both of the peripheral portion and the foot of the outer surface coating.

A flip chip includes a substrate, an electrode pad layer stacked over the substrate, a passivation layer stacked at both ends of the electrode pad layer, an under bump metallurgy (UBM) layer stacked over the electrode pad layer and the passivation layer, and a bump formed over the UBM layer. The width of an opening on which the passivation layer is not formed over the electrode pad layer is greater than the width of the bump. The flip chip can prevent a crack from being generated in the pad upon ultrasonic bonding.

An array substrate has a display area and a bonding area located on a side of the display area. The array substrate includes a base, a plurality of first transistors, a plurality of conductive pins and a plurality of conductive electrodes. The plurality of first transistors are disposed on a side of the base and located in the display area; a first transistor includes a first gate, a first source and a first drain. The plurality of conductive pins are disposed on the side of the base and located in the bonding area, and are disposed in a same layer as the first gate. The plurality of conductive electrodes are each disposed on a respective one of surfaces of the plurality of conductive pins away from the base.

In one embodiment, a method manufactures a semiconductor device including metallizations having peripheral portions with one or more underlying layers having marginal regions extending facing the peripheral portions. The method includes: providing a sacrificial layer to cover the marginal regions of the underlying layer, providing the metallizations while the marginal regions of the underlying layer are covered by the sacrificial layer, and removing the sacrificial layer so that the marginal regions of the underlying layer extend facing the peripheral portions in the absence of contact interface therebetween, thereby avoiding thermo-mechanical stresses.

A semiconductor die includes: a semiconductor substrate; a first contact pad structure above the semiconductor substrate, the first contact pad structure including a metal contact pad configured for electrical contact and a metal layer adjoining an underside of the metal contact pad and jutting out beyond an edge of the metal contact pad; and a first optical detection marker in a periphery of the first contact pad structure and having a different contrast than the metal contact pad. The first optical detection marker includes a region of the metal layer that is adjacent to the edge of the metal contact pad and unobstructed by the metal contact pad so as to be optically visible in a plan view of the semiconductor die. A method of producing the semiconductor die is also described.