A conductive terminal on an integrated circuit is provided. The conductive terminal includes a conductive pad, a dielectric layer, and a conductive via. The conductive pad is disposed on and electrically to the integrated circuit. The dielectric layer covers the integrated circuit and the conductive pad, the dielectric layer includes a plurality of contact openings arranged in array, and the conductive pad is partially exposed by the contact openings. The conductive via is disposed on the dielectric layer and electrically connected to the conductive pad through the contact openings. The conductive via includes a plurality of convex portions arranged in array. The convex portions are distributed on a top surface of the conductive via, and the convex portions are corresponding to the contact openings.

A method for fabricating a semiconductor die package includes: providing a semiconductor transistor die, the semiconductor transistor die having a first contact pad on a first lower main face and/or a second contact pad on an upper main face; fabricating a frontside electrical conductor onto the second contact pad and a backside electrical conductor onto the first contact pad; and applying an encapsulant covering the semiconductor die and at least a portion of the electrical conductor, wherein the frontside electrical conductor and/or the backside electrical conductor is fabricated by laser-assisted structuring of a metallic structure.

An integrated circuit includes a substrate, a pad electrode disposed on the substrate, and a passivation layer disposed on the pad electrode and including an organic insulating material. The integrated circuit further includes a bump electrode disposed on the passivation layer and connected to the pad electrode through a contact hole. The passivation layer includes an insulating portion having a first thickness and covering an adjacent edge region of the pad electrode and the substrate, and a bump portion having a second thickness, that is greater than the first thickness, and covering a center portion of the pad electrode.

There is set forth herein an optoelectrical device, comprising: a substrate; an interposer dielectric stack formed on the substrate, the interposer dielectric stack including a base interposer dielectric stack, a photonics device dielectric stack, and a bond layer that integrally bonds the photonics device dielectric stack to the base interposer dielectric stack. There is set forth herein a method comprising building an interposer base structure on a first wafer having a first substrate, including fabricating a plurality of through vias in the first substrate and fabricating within an interposer base dielectric stack formed on the first substrate one or more metallization layers; and building a photonics structure on a second wafer having a second substrate, including fabricating one or more photonics devices within a photonics device dielectric stack formed on the second substrate.

A pad is disposed on a substrate. A bump structure is disposed on the pad and electrically connected to the pad. The bump structure includes a first copper layer and a second copper layer sequentially stacked on the pad and a solder ball on the second copper layer. A first X-ray diffraction (XRD) peak intensity ratio of (111) plane to (200) plane of the first copper layer is greater than a second XRD peak intensity ratio of (111) plane to (200) plane of the second copper layer.

Methods for fabrication dielectric layers having conductive contact pads, and directly bonding the dielectric and conductive bonding surfaces of the dielectric layers. In some aspects, the method includes disposing a polish stop layer on dielectric bonding surfaces on top of a dielectric layer. A conductive layer is disposed on top of the polish stop layer and then polished to form conductive contact pads having polished conducting bonding surfaces. During the polishing process, the polish stop layer reduces rounding of dielectric edges and erosion of the dielectric bonding surfaces between closely spaced conductive bonding surfaces. The resulting polished dielectric and conductive bonding surfaces are directly bonded to dielectric and conductive bonding surfaces of another dielectric layer to form conductive interconnects.

A photo-emission semiconductor device superior in reliability is provided. The photo-emission semiconductor device includes a semiconductor layer, a light reflection layer provided on the semiconductor layer, and a protective layer formed by electroless plating to cover the light reflection layer. Therefore, even if the whole structure is reduced in size, the protective layer reliably covers the light reflection layer without gap.

Methods for forming a semiconductor device structure are provided. The method includes providing a first semiconductor wafer and a second semiconductor wafer. A first transistor is formed in a front-side of the first semiconductor wafer, and no devices are formed in the second semiconductor wafer. The method further includes bonding the front-side of the first semiconductor wafer to a backside of the second semiconductor wafer and thinning a front-side of the second semiconductor wafer. After thinning the second semiconductor wafer, a second transistor is formed in the front-side of the second semiconductor wafer. At least one first through substrate via (TSV) is formed in the second semiconductor wafer, and the first TSV directly contacts a conductive feature of the first semiconductor wafer.

A semiconductor package comprises a substrate, a pad, a first isolation layer, an interconnection layer, and a conductive post. The substrate has a first surface and a second surface opposite the first surface. The pad has a first portion and a second portion on the first surface of the substrate. The first isolation layer is disposed on the first surface and covers the first portion of the pad, and the first isolation layer has a top surface. The interconnection layer is disposed on the second portion of the pad and has a top surface. The conductive post is disposed on the top surface of the first isolation layer and on the top surface of the interconnection layer. The top surface of the first isolation layer and the top surface of the interconnection layer are substantially coplanar.

A package which comprises a chip carrier made of a first material, a body made of a second material differing from the first material and being arranged on the chip carrier so as to form a cavity, a semiconductor chip arranged at least partially in the cavity, and a laminate encapsulating at least one of at least part of the chip carrier, at least part of the body and at least part of the semiconductor chip.