Patent classifications
H01L2224/05617
Display module and manufacturing method as the same
A display module is disclosed. The display module includes a pixel that includes: first to third self-luminescence elements that are configured to emit light of an ultraviolet wavelength range; first to third color conversion layers respectively corresponding to light emitting surfaces of the first to third self-luminescence elements; a first color filter and a second color filter respectively corresponding to the first color conversion layer and the second color conversion layer; a transparent resin layer corresponding to the third color conversion layer and disposed on a same plane as a plane at which the first color filter and the second color filter are positioned; a transparent cover layer that covers the first color filter, the second color filter, and the transparent resin layer; and an ultraviolet (UV) cutoff filter that covers the transparent cover layer.
Bonded assembly including interconnect-level bonding pads and methods of forming the same
A bonded assembly includes a first semiconductor die that includes first metallic bonding structures embedded within a first bonding-level dielectric layer, and a second semiconductor die that includes second metallic bonding structures embedded within a second bonding-level dielectric layer and bonded to the first metallic bonding structures by metal-to-metal bonding. One of the first metallic bonding structures a pad portion, and a via portion located between the pad portion and a first semiconductor device in the first semiconductor die, the via portion having second tapered sidewalls.
Semiconductor package including underfill and method of forming the same
A semiconductor package includes a first semiconductor chip on a lower structure. A first underfill is between the first semiconductor chip and the lower structure. The first underfill includes a first portion adjacent to a center region of the first semiconductor chip, and a second portion adjacent to an edge region of the first semiconductor chip. The second portion has a higher degree of cure than the first portion. A plurality of inner connection terminals is between the first semiconductor chip and the lower structure. The plurality of inner connection terminals extends in the first underfill.
Phase change interconnects and methods for forming the same
A structure of a semiconductor package is disclosed. The structure includes a first substrate including a first interconnect structure. The structure includes a second substrate including a second interconnect structure, the second substrate bonded to the first substrate. The structure includes a connection pad interposed between the first interconnect structure and the second interconnect structure. The connection pad includes a material configured to switch between a high resistance state and a low resistance state. The material of the connection pad includes a phase change material.