A silicon carbide device includes a silicon carbide substrate, a contact layer including nickel, silicon and aluminum, a barrier layer structure including titanium and tungsten, and a metallization layer including copper. The contact layer is located on the silicon carbide substrate. The contact layer is located between the silicon carbide substrate and at least a part of the barrier layer structure. The barrier layer structure is located between the silicon carbide substrate and the metallization layer.

One aspect of the invention is a method of manufacturing a connection structure, including disposing an adhesive layer between a first electronic member including a first substrate and a first electrode formed on the first substrate and a second electronic member including a second substrate and a second electrode formed on the second substrate, and pressure-bonding the first electronic member and the second electronic member via the adhesive layer such that the first electrode and the second electrode are electrically connected to each other, wherein the first electronic member further including an insulating layer formed on a side of the first electrode opposite to the first substrate, and the adhesive layer including: a first conductive particle being a dendritic conductive particle; and a second conductive particle being a conductive particle other than the first conductive particle and having a non-conductive core and a conductive layer provided on the core.

One aspect of the invention is a method of manufacturing a connection structure, including disposing an adhesive layer between a first electronic member including a first substrate and a first electrode formed on the first substrate and a second electronic member including a second substrate and a second electrode formed on the second substrate, and pressure-bonding the first electronic member and the second electronic member via the adhesive layer such that the first electrode and the second electrode are electrically connected to each other, wherein the first electronic member further including an insulating layer formed on a side of the first electrode opposite to the first substrate, and the adhesive layer including: a first conductive particle being a dendritic conductive particle; and a second conductive particle being a conductive particle other than the first conductive particle and having a non-conductive core and a conductive layer provided on the core.

A method of fabricating an under-bump metallurgy (UBM) structure that is free of gold processing includes forming a titanium layer on top of a far back of line (FBEOL) of a semiconductor. A first copper layer is formed on top of the titanium layer. A photoresist (PR) layer is formed on top of the first copper layer between traces of the FBEOL to provide a cavity to the FBEOL traces. A top copper layer is formed on top of the first copper layer. A protective surface layer (PSL) is formed on top of the top copper layer.

A method of fabricating an under-bump metallurgy (UBM) structure that is free of gold processing includes forming a titanium layer on top of a far back of line (FBEOL) of a semiconductor. A first copper layer is formed on top of the titanium layer. A photoresist (PR) layer is formed on top of the first copper layer between traces of the FBEOL to provide a cavity to the FBEOL traces. A top copper layer is formed on top of the first copper layer. A protective surface layer (PSL) is formed on top of the top copper layer.

A nucleation suppression layer including a self-assembly material can be formed on a surface of a bonding dielectric layer without depositing the self-assembly material on physically exposed surfaces of first metal bonding pads of a first semiconductor die. Metallic liners including a second metal can be formed on the physically exposed surfaces of the metal bonding pads without depositing the second metal on the nucleation suppression layer. The first semiconductor die is bonded to a second semiconductor die by inducing metal-to-metal bonding between mating pairs of the first metal bonding pads and second metal bonding pads of the second semiconductor die.

A nucleation suppression layer including a self-assembly material can be formed on a surface of a bonding dielectric layer without depositing the self-assembly material on physically exposed surfaces of first metal bonding pads of a first semiconductor die. Metallic liners including a second metal can be formed on the physically exposed surfaces of the metal bonding pads without depositing the second metal on the nucleation suppression layer. The first semiconductor die is bonded to a second semiconductor die by inducing metal-to-metal bonding between mating pairs of the first metal bonding pads and second metal bonding pads of the second semiconductor die.

The present application provides a method for fabricating a semiconductor device. The method includes providing a carrier substrate, forming through semiconductor vias in the carrier substrate for thermally conducting heat, forming a bonding layer on the carrier substrate, providing a first die structure including through semiconductor vias, forming an intervening bonding layer on the first die structure, bonding the first die structure onto the bonding layer through the intervening bonding layer, and bonding a second die structure onto the first die structure. The carrier substrate, the through semiconductor vias, and the bonding layer together configure a carrier structure. The second die structure and the first die structure are electrically coupled by the through semiconductor vias.

The present application provides a method for fabricating a semiconductor device. The method includes providing a carrier substrate, forming through semiconductor vias in the carrier substrate for thermally conducting heat, forming a bonding layer on the carrier substrate, providing a first die structure including through semiconductor vias, forming an intervening bonding layer on the first die structure, bonding the first die structure onto the bonding layer through the intervening bonding layer, and bonding a second die structure onto the first die structure. The carrier substrate, the through semiconductor vias, and the bonding layer together configure a carrier structure. The second die structure and the first die structure are electrically coupled by the through semiconductor vias.

An integrated circuit (IC) package product, e.g., system-on-chip (SoC) or system-in-package (SiP) product, may include at least one integrated inductor having a core magnetic field (B field) that extends parallel to the substrate major plane of at least one die or chiplet included in or mounted to the product, which may reduce the eddy currents within each die/chiplet substrate, and thereby reduce energy loss of the indictor. The IC package product may include a horizontally-extending IC package substrate, a horizontally-extending die mount base arranged on the IC package substrate, at least one die mounted to the die mount base in a vertical orientation, and an integrated inductor having a B field extending in a vertical direction parallel to the silicon substrate of each vertically-mounted die, thereby providing a reduced substrate loss in the integrated inductor, which provides an increased quality factor (Q) of the inductor.