A bonded device structure including a first substrate having a first set of conductive contact structures, preferably connected to a device or circuit, and having a first non-metallic region adjacent to the contact structures on the first substrate, a second substrate having a second set of conductive contact structures, preferably connected to a device or circuit, and having a second non-metallic region adjacent to the contact structures on the second substrate, and a contact-bonded interface between the first and second set of contact structures formed by contact bonding of the first non-metallic region to the second non-metallic region. The contact structures include elongated contact features, such as individual lines or lines connected in a grid, that are non-parallel on the two substrates, making contact at intersections. Alignment tolerances are thus improved while minimizing dishing and parasitic capacitance.

A surface treatment solution includes a fluoride source; a first solvent; and a water transforming agent to transform water produced during wafer surface treatment into a second solvent, which can be the same as, or different from, the first solvent. The solution can be used, for example, in surface preparation for wafers having a backend including an electrical interconnect that includes aluminum or an aluminum alloy.

An integrated circuit (IC) die structure comprises a substrate material comprising silicon. Integrated circuitry is over a first side of the substrate material. A composite layer is in direct contact with a second side of the substrate material. The second side is opposite the first side. The composite layer comprises a first constituent material associated with a first linear coefficient of thermal expansion (CTE), and a first thermal conductivity exceeding that of the substrate. The composite layer also comprises a second constituent material associated with a second CTE that is lower than the first, and a second thermal conductivity exceeding that of the substrate.

A Cu.sub.3Sn electrical interconnect and method of making same in an electrical device, such as for hybrid bond 3D-integration of the electrical device with one or more other electrical devices. The method of forming the Cu.sub.3Sn electrical interconnect includes: depositing a Sn layer in the via hole; depositing a Cu layer atop and in contact with the Sn layer; and heating the Sn layer and the Cu layer such that the Sn and Cu layers diffuse together to form a Cu.sub.3Sn interconnect in the via hole. During the heating, a diffusion front between the Sn and Cu layers moves in a direction toward the Cu layer as initially deposited, such that any remaining Cu layer or any voids formed during the diffusion are at an upper region of the formed Cu.sub.3Sn interconnect in the via hole, thereby allowing such voids or remaining material to be easily removed.

A Cu.sub.3Sn electrical interconnect and method of making same in an electrical device, such as for hybrid bond 3D-integration of the electrical device with one or more other electrical devices. The method of forming the Cu.sub.3Sn electrical interconnect includes: depositing a Sn layer in the via hole; depositing a Cu layer atop and in contact with the Sn layer; and heating the Sn layer and the Cu layer such that the Sn and Cu layers diffuse together to form a Cu.sub.3Sn interconnect in the via hole. During the heating, a diffusion front between the Sn and Cu layers moves in a direction toward the Cu layer as initially deposited, such that any remaining Cu layer or any voids formed during the diffusion are at an upper region of the formed Cu.sub.3Sn interconnect in the via hole, thereby allowing such voids or remaining material to be easily removed.

A method of forming a conductive material on a semiconductor device. The method comprises removing at least a portion of a conductive pad within an aperture in a dielectric material over a substrate. The method further comprises forming a seed material at least within a bottom of the aperture and over the dielectric material, forming a protective material over the seed material within the aperture, and forming a conductive pillar in contact with the seed material through an opening in the protective material over surfaces of the seed material within the aperture. A method of forming an electrical connection between adjacent semiconductor devices, and a semiconductor device, are also described.

A method of forming a conductive material on a semiconductor device. The method comprises removing at least a portion of a conductive pad within an aperture in a dielectric material over a substrate. The method further comprises forming a seed material at least within a bottom of the aperture and over the dielectric material, forming a protective material over the seed material within the aperture, and forming a conductive pillar in contact with the seed material through an opening in the protective material over surfaces of the seed material within the aperture. A method of forming an electrical connection between adjacent semiconductor devices, and a semiconductor device, are also described.

The present disclosure provides a display panel and a display device. A distance from a surface of a first conductive adhesive layer close to a first pin, electrically connecting the first conductive pad and the first pin, to the substrate is different from a distance of a surface of a second conductive adhesive layer electrically connected to the second conductive pad and the second pin to the substrate, to compensate for a height difference caused by the partial warpage of the pins on the drive chip when binding a drive chip, so as to ensure that the drive chip can be well bonded to the display panel.

A substrate comprising a solid glass core having a first surface and a second surface opposed to the first surface; multiple conductors extending through the solid glass core beginning at the first surface and ending at the second surface, wherein one of the conductors has a third surface and a fourth surface, wherein the third surface and the first surface are substantially coplanar, wherein the second surface and the fourth surface are substantially coplanar, wherein one of the conductors comprise a copper-tungsten alloy material, wherein the solid glass core is directly contact with the conductor; and a first dielectric layer and a first metal layer formed at the first surface, wherein the first metal layer at the first surface is electrically coupled with one of the conductors.

A substrate comprising a solid glass core having a first surface and a second surface opposed to the first surface; multiple conductors extending through the solid glass core beginning at the first surface and ending at the second surface, wherein one of the conductors has a third surface and a fourth surface, wherein the third surface and the first surface are substantially coplanar, wherein the second surface and the fourth surface are substantially coplanar, wherein one of the conductors comprise a copper-tungsten alloy material, wherein the solid glass core is directly contact with the conductor; and a first dielectric layer and a first metal layer formed at the first surface, wherein the first metal layer at the first surface is electrically coupled with one of the conductors.