Methods and architectures for shallow fiducial and metal defined pad designs. Embodiments utilize a thinnable dielectric process. The architecture includes a substrate comprising a dielectric material with one or more conductive contacts on the surface. A layer of a thinnable dielectric or non-conductive material is over the substrate and over the one or more conductive contacts. The layer of dielectric or non-conductive material has a thinned region around individual conductive contacts. The thinned region has a thickness of 4 to 5 microns.

Structures for an electrical interconnection and methods of forming a structure for an electrical interconnection. The structure comprises a bond pad and an electrical interconnection including a pillar positioned on a portion of the bond pad. The pillar includes a first section and a second section between the first section and the portion of the bond pad. The second section has a cross section with a perimeter having a non-round closed shape, and the second section is positioned acentric relative to the first section.

A wafer level chip scale package includes a semiconductor substrate having a first thickness, an input-output pad formed on the semiconductor substrate, a front metal layer having a second thickness formed on the input-output pad, a back metal layer having a third thickness formed on a bottom of the semiconductor substrate, and a metal bump formed on the semiconductor substrate.