An electronic device and a manufacturing method thereof. As non-limiting examples, various aspects of this disclosure provide an electronic device having a top side pin array, for example which may be utilized for three-dimensional stacking, and a method for manufacturing such an electronic device.

An electronic device and a manufacturing method thereof. As non-limiting examples, various aspects of this disclosure provide an electronic device having a top side pin array, for example which may be utilized for three-dimensional stacking, and a method for manufacturing such an electronic device.

A semiconductor package includes a semiconductor chip comprising a first surface and a second surface, a redistribution layer on the first surface of the semiconductor chip, an under bump metal (UBM) layer on the redistribution layer, and a solder bump on the UBM layer, and the solder bump covers both outer side surfaces of the UBM layer.

A semiconductor package includes a semiconductor chip comprising a first surface and a second surface, a redistribution layer on the first surface of the semiconductor chip, an under bump metal (UBM) layer on the redistribution layer, and a solder bump on the UBM layer, and the solder bump covers both outer side surfaces of the UBM layer.

In a general aspect, a method can include forming a first conductive metal layer including a common gate conductor, and coupling a plurality of semiconductor die to the common gate conductor of the first conductive metal layer where the plurality of semiconductor die include a first silicon carbide die and a second silicon carbide die. The method can include encapsulating at least a portion of the first conductive metal layer and the semiconductor die within an insulator where the first conductive metal layer includes a first conductive path between the common gate conductor and a die gate conductor of the first silicon carbide die, and a second conductive path between the common gate conductor and a die gate conductor of the second silicon carbide die. The first conductive path can have a length substantially equal to a length of the second conductive path.

In a general aspect, a method can include forming a first conductive metal layer including a common gate conductor, and coupling a plurality of semiconductor die to the common gate conductor of the first conductive metal layer where the plurality of semiconductor die include a first silicon carbide die and a second silicon carbide die. The method can include encapsulating at least a portion of the first conductive metal layer and the semiconductor die within an insulator where the first conductive metal layer includes a first conductive path between the common gate conductor and a die gate conductor of the first silicon carbide die, and a second conductive path between the common gate conductor and a die gate conductor of the second silicon carbide die. The first conductive path can have a length substantially equal to a length of the second conductive path.

An electronic device and a manufacturing method thereof. As non-limiting examples, various aspects of this disclosure provide an electronic device having a top side pin array, for example which may be utilized for three-dimensional stacking, and a method for manufacturing such an electronic device.

An electronic device and a manufacturing method thereof. As non-limiting examples, various aspects of this disclosure provide an electronic device having a top side pin array, for example which may be utilized for three-dimensional stacking, and a method for manufacturing such an electronic device.

In some examples, an electronic device comprises a first component having a surface, a second component having a surface, and a bond layer positioned between the surfaces of the first and second components to couple the first and second components to each other. The bond layer includes a set of metallic nanowires and a dielectric portion. The dielectric portion comprises a polymer matrix and dielectric nanoparticles.

In some examples, an electronic device comprises a first component having a surface, a second component having a surface, and a bond layer positioned between the surfaces of the first and second components to couple the first and second components to each other. The bond layer includes a set of metallic nanowires and a dielectric portion. The dielectric portion comprises a polymer matrix and dielectric nanoparticles.