A semiconductor device including a first die and a second die bonded to one another. The first die includes a first passivation layer over a substrate, and first bond pads in the first passivation layer. The second die includes a second passivation layer, which may be bonded to the first passivation layer, and second bond pads in the second passivation layer, which may be bonded to the first bond pads. The second bond pads include inner bond pads and outer bond pads. The outer bond pads may have a greater diameter than the inner bond pads as well as the first bond pads.

Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface, and a die secured to the package substrate, wherein the die has a first surface and an opposing second surface, the die has first conductive contacts at the first surface and second conductive contacts at the second surface, and the first conductive contacts are coupled to conductive pathways in the package substrate by first non-solder interconnects.

Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate including a dielectric material having a first surface and an opposing second surface, a first photodefinable material on at least a portion of the second surface, and a second photodefinable material on at least a portion of the first photodefinable material, wherein the second photodefinable material has a different material composition than the first photodefinable material.

A semiconductor package and a fabrication method of the semiconductor package are disclosed. First and second redistribution layer patterns are formed on a semiconductor substrate including a chip region and a scribe lane region to provide a bonding pad portion and an edge pad portion, respectively. A polymer pattern is formed to reveal the bonding pad portion and a portion of the edge pad portion. A dicing line is set on the scribe lane region. A stealth dicing process is performed along the dicing line to separate a semiconductor chip including the bonding pad portion from the semiconductor substrate. The semiconductor chip is disposed on a package substrate. A bonding wire is formed to connect the bonding pad portion to the package substrate. The bonding wire is supported by an edge of the polymer pattern to be spaced apart from the revealed portion of the edge pad portion.

Semiconductor devices may include a first semiconductor chip, a first redistribution layer on a bottom surface of the first semiconductor chip, a second semiconductor chip on the first semiconductor chip, a second redistribution layer on a bottom surface of the second semiconductor chip, a mold layer extending on sidewalls of the first and second semiconductor chips and on the bottom surface of the first semiconductor chip, and an external terminal extending through the mold layer and electrically connected to the first redistribution layer. The second redistribution layer may include an exposed portion. The first redistribution layer may include a first conductive pattern electrically connected to the first semiconductor chip and a second conductive pattern electrically insulated from the first semiconductor chip. The exposed portion of the second redistribution layer and the second conductive pattern of the first redistribution layer may be electrically connected by a first connection wire.

A display device including a display panel including a base layer, a circuit layer disposed on the base layer, and a pad part having a plurality of pads disposed on the base layer; and a driving chip disposed on the pad part and including a plurality of chip pads. The plurality of pads include a first pad having a smaller area than a corresponding chip pad among the plurality of chip pads and a second pad electrically connected to the circuit layer.

A circuit structure including a pad assembly, a bonding pad assembly, and a bonding assembly is provided. The pad assembly includes a first pad, a second pad, and a third pad which are separated from one another. The bonding pad assembly is located on one side of the pad assembly and includes a first bonding pad. The bonding assembly includes a first bonding wire, a second bonding wire, and a plurality of bonding members. The first bonding wire is connected to the first bonding pad and the first pad. The second bonding wire is connected to the first bonding pad and the third pad. The bonding members are connected among the first pad, the second pad, and the third pad. The circuit structure provided here may have an improved wire bonding efficiency and an increased distribution density of bonding points, and the number of bonding wires may be reduced.

Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate including a dielectric material having a first surface and an opposing second surface, a first photodefinable material on at least a portion of the second surface, and a second photodefinable material on at least a portion of the first photodefinable material, wherein the second photodefinable material has a different material composition than the first photodefinable material.

A semiconductor device includes a first substrate having a first surface, and a second substrate having a second surface in contact with the first surface. The first substrate includes a first circuit, a first electrode having a first connection end on the first surface, and a first auxiliary electrode having a second connection end on the first surface. The first electrode is connected to the first circuit inside the first substrate, and the first auxiliary electrode is connected to the first electrode. The second substrate includes a second circuit and a second electrode having a third connection end on the second surface. The second electrode is connected to the second circuit. The third connection end is connected directly with the first connection end and the second connection end. The second electrode is connected directly with the first electrode and through the first auxiliary electrode to the first electrode.

A driving chip and a display panel are provided. The display panel includes the driving chip, and a plurality of first bonding pads and a plurality of second bonding pads disposed at two opposite sides of the driving chip. The driving chip includes a group of first input leads and a group of second input leads. There is an interval between the group of first input leads and the group of second input leads. The group of first input leads is disposed near the first bonding pads, and the group of second input leads is disposed near the second bonding pads.