The embodiments of the present invention discloses an arrangement of bond pads on an integrated circuit chip. The integrated circuit chip includes: a first row of bond pads; and a second row of bond pads, wherein bond pads in the first row are positioned alternately with bond pads in the second row, and a short side of the bond pads in the first row and the second row is parallel to a long side of the integrated circuit chip. With this arrangement of bond pads on the integrated circuit chip, the bond pads may occupy a reduced area of a surface of the integrated circuit chip.

Semiconductor devices can be formed over a semiconductor substrate, and interconnect-level dielectric material layers embedding metal interconnect structures can be formed thereupon. In one embodiment, a pad-connection-via-level dielectric material layer, a proximal dielectric diffusion barrier layer, and a pad-level dielectric material layer can be formed. Bonding pads surrounded by dielectric diffusion barrier portions can be formed in the pad-level dielectric material layer. In another embodiment, a layer stack of a proximal dielectric diffusion barrier layer and a pad-and-via-level dielectric material layer can be formed. Integrated pad and via cavities can be formed through the pad-and-via-level dielectric material layer, and can be filled with bonding pads containing dielectric diffusion barrier portions and integrated pad and via structures.

Semiconductor devices can be formed over a semiconductor substrate, and interconnect-level dielectric material layers embedding metal interconnect structures can be formed thereupon. In one embodiment, a pad-connection-via-level dielectric material layer, a proximal dielectric diffusion barrier layer, and a pad-level dielectric material layer can be formed. Bonding pads surrounded by dielectric diffusion barrier portions can be formed in the pad-level dielectric material layer. In another embodiment, a layer stack of a proximal dielectric diffusion barrier layer and a pad-and-via-level dielectric material layer can be formed. Integrated pad and via cavities can be formed through the pad-and-via-level dielectric material layer, and can be filled with bonding pads containing dielectric diffusion barrier portions and integrated pad and via structures.

A first semiconductor device includes: a first wiring layer including a first interlayer insulating film, a first electrode pad, and a first dummy electrode, the first electrode pad being embedded in the first interlayer insulating film and having one surface located on same plane as one surface of the first interlayer insulating film, and the first dummy electrode being embedded in the first interlayer insulating film, having one surface located on same plane as the one surface of the first interlayer insulating film, and being disposed around the first electrode pad; and a second wiring layer including a second interlayer insulating film, a second electrode pad, and a second dummy electrode, the second electrode pad being embedded in the second interlayer insulating film, having one surface located on same surface as one surface of the second interlayer insulating film, and being bonded to the first electrode pad, and the second dummy electrode having one surface located on same plane as the surface located closer to the first interlayer insulating film of the second interlayer insulating film, being disposed around the second electrode pad, and being bonded to the first dummy electrode. A second semiconductor device includes: a first semiconductor section including a first electrode, the first electrode being formed on a surface located closer to a bonding interface and extending in a first direction; and a second semiconductor section including a second electrode and disposed to be bonded to the first semiconductor section at the bonding interface, the second electrode being bonded to the first electrode and extending in a second direction that intersects with the first direction.

A display device includes a substrate including a display area to display an image and a pad area positioned around the display area; a first pad unit disposed on the pad area, and including a first terminal region having a plurality of first pad terminals arranged in a first direction; and a printed circuit board including a base film and a second pad unit positioned at one side of the base film, the second pad unit being coupled with the first pad unit by electrically connecting with the plurality of first pad terminals. Each of the plurality of first pad terminals includes: at least three first connection pad terminals arranged in a first row disposed at a first angle larger than 0° and smaller than 90° relative to the first direction, the plurality of first connection pad terminals being in electrically connecting with the second pad unit of the printed circuit board through a plurality of conductive balls; a plurality of second connection pad terminals spaced apart from the plurality of first connection pad terminals, and arranged in a second row disposed at a second angle larger than 0° and smaller than 90° relative to the first direction, the plurality of second connection pad terminals being in electrically connecting with the second pad unit of the printed circuit board through another plurality of conductive balls; and a plurality of first dummy pad terminals disposed between pairs of adjacent first connection pad terminals of the first connection pad terminals.

A semiconductor device, an integrated fan-out package and a method of forming the same are disclosed. In some embodiments, a semiconductor device includes a substrate, a conductive layer, a passivation layer and a bump structure. The substrate has at least one electronic component therein. The conductive layer has a plurality of lines patterns over and electrically connected to the at least one electronic component. The passivation layer is over the conductive layer. The bump structure has a plurality of protruding parts penetrating through the passivation layer and electrically connected to the lines patterns of the conductive layer.

Semiconductor devices and methods of manufacture are provided wherein a metallization layer is located over a substrate, and a power grid line is located within the metallization layer. A signal pad is located within the metallization layer and the signal pad is surrounded by the power grid line. A signal external connection is electrically connected to the signal pad.

A semiconductor device includes a first wafer including a row decoder region in which a plurality of pass transistors are arranged in a row direction and a column direction; a plurality of first bonding pads, respectively coupled to the plurality of pass transistors that are disposed in a plurality of rows on one surface of the first wafer in the row decoder region; and a plurality of second bonding pads disposed on the one surface of the first wafer in the row decoder region, wherein the plurality of second bonding pads are disposed in a different row from the plurality of first bonding pads and are offset in the row direction with respect to the plurality of first bonding pads.

A semiconductor device includes a substrate, a semiconductor chip, a plurality of bonding pads on a surface of the semiconductor chip, a plurality of probe pads on a surface of the semiconductor chip, a plurality of connection pads on a surface of the substrate, and a plurality of bonding wires that electrically connect the bonding pads and the connection pads. The plurality of bonding pads include a first bonding pad and a second bonding pad, the plurality of probe pads include a first probe pad and a second probe pad, and a part of the first probe pad is disposed between the second bonding pad and the second probe pad.

Bonded wafer device structures, such as a wafer-on-wafer (WoW) structures, and methods of fabricating bonded wafer device structures, including an array of contact pads formed in an interconnect level of at least one wafer of the bonded wafer device structure. The array of contact pads formed in an interconnect level of at least one wafer may have an array pattern that corresponds to an array pattern of contact pads that is subsequently formed over a surface of the bonded wafer structure. The array of contact pads formed in an interconnect level of at least one wafer of the bonded wafer device structure may enable improved testing of individual wafers, including circuit probe testing, prior to the wafer being stacked and bonded to one or more additional wafers to form a bonded wafer structure.