A semiconductor device with improved reliability is provided. The semiconductor device is characterized by its embodiments in that sloped portions are formed on connection parts between a pad and a lead-out wiring portion, respectively. This feature suppresses crack formation in a coating area where a part of the pad is covered with a surface protective film.

A semiconductor device includes a first substrate and a second substrate that is stacked on a first surface of the first substrate in a stacking direction and includes a second surface facing the first surface. A plurality of first terminals is provided on the first surface of the first substrate. A plurality of second terminals is provided on the second surface of the second substrate. A plurality of metallic portions is respectively provided between the plurality of first terminals and the plurality of second terminals. In a cross-section substantially perpendicular to the stacking direction, at least one of (i) each of the plurality of first terminals or (ii) each of the plurality of second terminals (a) includes a recessed portion in a first direction toward an adjacent first terminal or second terminal or (b) includes a projecting portion in a second direction intersecting with the first direction.

A semiconductor device includes a first substrate and a second substrate that is stacked on a first surface of the first substrate in a stacking direction and includes a second surface facing the first surface. A plurality of first terminals is provided on the first surface of the first substrate. A plurality of second terminals is provided on the second surface of the second substrate. A plurality of metallic portions is respectively provided between the plurality of first terminals and the plurality of second terminals. In a cross-section substantially perpendicular to the stacking direction, at least one of (i) each of the plurality of first terminals or (ii) each of the plurality of second terminals (a) includes a recessed portion in a first direction toward an adjacent first terminal or second terminal or (b) includes a projecting portion in a second direction intersecting with the first direction.

Semiconductor devices and methods of manufacture are provided wherein a metallization layer is located over a substrate, and a power grid line is located within the metallization layer. A signal pad is located within the metallization layer and the signal pad is surrounded by the power grid line. A signal external connection is electrically connected to the signal pad.

A bond-wire system including a wire bond that is deflected above a dielectric ridge at a die edge. The deflected wire bond allows for both a lowered Z-profile and a reduced X-Y footprint. The bond-wire system may include a stacked-die configuration where a stacked die is wire bonded and the stacked-die bond wire is deflected above a dielectric ridge at the stacked die edge.

An array substrate and a display panel are proposed. Each of the signal conversion lines of the array substrate extends in the first direction, and connects two connection terminals adjacent to the each of signal conversion lines. Projections of the connection terminals on the reference plane in the second direction do not overlap. In this manner, the design that the adjacent connection terminals are interlaced can increase the spacing between the adjacent connection terminals, thus resolving the problem that the spacing between connection terminals on the array substrate is excessively small and short circuiting tends to happen when bonding to cause poor bonding in the related art.

The present disclosure relates to a method of hybrid molecular bonding of a first surface of a first electronic circuit to a second surface of a second electronic circuit. The first electronic circuit includes first conductive pads exposed on the first surface and first conductive tracks exposed on the first surface. The length of each first track is equal to at least five times the width of the first track, the first tracks delivering the reference voltage to the first electronic circuit. The second electronic circuit includes second conductive pads exposed on the second surface and second conductive tracks exposed on the second surface. The length of each second track is equal to at least five times the length of the second track. The method comprises placing into contact the first pads with the second pads and the first tracks with the second tracks.

A semiconductor chip having a core region and an I/O region which surrounds the core region is provided with a plurality of external connection pads connected to I/O cells. The plurality of external connection pads include a first pad group comprised of the external connection pads connected to the same node, and a second pad group comprised of the external connection pads connected to respective different nodes. In first and second pad groups, the external connection pads are arranged in an X direction along an external side of the semiconductor chip, and a pad arrangement pitch in the first pad group is smaller than that in the second pad group.

A semiconductor device includes a semiconductor substrate SB and a wiring structure formed on a main surface of the semiconductor substrate SB. The uppermost first wiring layer among a plurality of wiring layers included in the wiring structure includes a pad PD, and the pad PD has a first region for bonding a copper wire and a second region for bringing a probe into contact with the pad. A second wiring layer that is lower by one layer than the first wiring layer among the plurality of wiring layers included in the wiring structure includes a wiring line M6 arranged immediately below the pad PD, the wiring line M6 is arranged immediately below a region other than the first region of the pad PD, and no conductor pattern in the same layer as a layer of the wiring line M6 belong is formed immediately below the first region of the pad PD.

A semiconductor device includes a semiconductor substrate SB and a wiring structure formed on a main surface of the semiconductor substrate SB. The uppermost first wiring layer among a plurality of wiring layers included in the wiring structure includes a pad PD, and the pad PD has a first region for bonding a copper wire and a second region for bringing a probe into contact with the pad. A second wiring layer that is lower by one layer than the first wiring layer among the plurality of wiring layers included in the wiring structure includes a wiring line M6 arranged immediately below the pad PD, the wiring line M6 is arranged immediately below a region other than the first region of the pad PD, and no conductor pattern in the same layer as a layer of the wiring line M6 belong is formed immediately below the first region of the pad PD.