Methods for hybrid bonding include depositing and patterning a dielectric layer on a substrate to form openings in the dielectric layer, depositing a barrier layer over the dielectric layer and within a first portion of the openings, and depositing a conductive structure over the barrier layer and within a second portion of the openings not occupied by the barrier layer, at least a portion of the conductive structure in the second portion of the openings coupled or contacting electrical circuitry within the substrate. The conductive structure is polished to reveal portions of the barrier layer deposited over the dielectric layer and not in the second portion of the openings. Further, the barrier layer is polished with a selective polish to reveal a bonding surface on or at the dielectric layer.

An insulating transformer comprising: an insulation layer; a transformer including a first coil embedded in the insulation layer and a second coil; and a capacitor including a first capacitor electrode and a second capacitor electrode, the first capacitor electrode being arranged between the first coil and the second coil and connected to a first ground terminal, and the second capacitor electrode being arranged between the first capacitor electrode and the second coil and connected to a second ground terminal.

A semiconductor device includes a semiconductor substrate, a power transistor formed in the semiconductor substrate, the power transistor including an active area in which one or more power transistor cells are formed, a first metal pad formed above the semiconductor substrate and covering substantially all of the active area of the power transistor, the first metal pad being electrically connected to a source or emitter region in the active area of the power transistor, the first metal pad including an interior region laterally surrounded by a peripheral region, the peripheral region being thicker than the interior region, and a first interconnect plate or a semiconductor die attached to the interior region of the first metal pad by a die attach material. Corresponding methods of manufacture are also described.

Solid-state lighting devices including light-emitting diodes (LEDs) and more particularly LED chips with interconnect structures are disclosed. LED chips are provided that include first interconnects electrically coupled to an n-type layer and second interconnects electrically connected to a p-type layer. Configurations of the first and second interconnects are provided that may improve current spreading by reducing localized areas of current crowding within LED chips. Various configurations are disclosed that include collectively formed symmetric patterns of the first and second interconnects, diameters of certain ones of either the first or second interconnects that vary based on their relative positions in LED chips, and spacings of the second interconnects that vary based on their distances from the first interconnects. In this regard, LED chips are disclosed with improved current spreading as well as higher lumen outputs and efficiencies.

A semiconductor package includes a lower chip, an upper chip on the lower chip, and an adhesive layer between the lower chip and the upper chip. The lower chip has first through silicon vias (TSVs) and pads on an upper surface thereof. The pads are connected to the first TSVs, respectively. The upper chip includes bumps on a lower surface thereof. The bumps are bonded to the pads. Vertical centerlines of the bumps are aligned with vertical centerlines of the first TSVs, respectively. The vertical centerlines of the bumps are offset from the vertical centerlines of the pads, respectively, in a peripheral region of the lower chip.

This isolation transformer includes: an isolation layer; a transformer having a first coil and a second coil; and a capacitor having a first capacitor electrode and a second capacitor electrode disposed between the first coil and the second coil. The isolation layer includes a first isolation film in which the first coil is embedded, a second isolation film on the upper surface of the first isolation film, a protective film on the upper surface of the second isolation film, a third isolation film on the upper surface of the protective film, a fourth isolation film on the upper surface of the third isolation film, and a fifth isolation film on the upper surface of the fourth isolation film. The second capacitor electrode is formed between the third isolation film and the fourth isolation film. The second coil is formed between the fourth isolation film and the fifth isolation film.

An isolation transformer includes an insulation layer, a transformer, and a capacitor. The transformer includes first and second coils separated from each other in a thickness-wise direction of the insulation layer. The capacitor includes a first capacitor electrode and a second capacitor electrode. The insulation layer includes thin films and interlayer insulation films alternately stacked in the direction. The thin films include first and second thin films separated from each other in the direction. The interlayer insulation films include a first interlayer insulation film located next to the first thin film in the direction and a second interlayer insulation film located next to the second thin film in the direction. The first capacitor electrode is formed between the first thin film and the first interlayer insulation film. The second capacitor electrode is formed between the second thin film and the second interlayer insulation film.

A semiconductor device includes: a semiconductor layer; first and second transistors; one or more first source pads and a first gate pad of the first transistor in a first region of the upper surface of the semiconductor layer; and one or more second source pads and a second gate pad of the second transistor in a second region of the upper surface adjacent to the first region in a plan view of the semiconductor layer. In a plan view of the semiconductor layer, a virtual straight line connecting the centers of the first and second gate pads passes through the center of the semiconductor layer and forms a 45 degree angle with each side of the semiconductor layer. An upper surface boundary line between the first and second regions monotonically changes in the directions of extension of the longer and shorter sides of the semiconductor layer.

A display apparatus includes a printed circuit board including first to fourth output pad regions and a flexible circuit board having a first end connected to a display panel and a second end connected to the printed circuit board. The first output pad region includes a 1.sup.st-1.sup.st output pad group and a 1.sup.st-2.sup.nd output pad group, the second output pad region includes a 2.sup.nd-1.sup.st output pad group and a 2.sup.nd-2.sup.nd output pad group, the fourth output pad region includes a 4.sup.th-1.sup.st output pad group and a 4.sup.th-2.sup.nd output pad group, and the printed circuit board includes a first input terminal electrically connected to the 1.sup.st-1.sup.st output pad group, a second input terminal electrically connected to the 2.sup.nd-2.sup.nd output pad group, a third input terminal electrically connected to the first input terminal, and a fourth input terminal electrically connected to the 4.sup.th-2.sup.nd output pad group.

An electronic device, including an array substrate, a pad portion disposed on the array substrate, and an integrated circuit disposed on the pad portion and comprising a bump portion. The pad portion includes a first sub-pad unit including a first pad having an inclined shape and a second sub-pad unit including a second pad having an inclined shape. The first pad and the second pad are symmetrically arranged with respect to an imaginary line that divides the pad portion. The pad portion is electrically connected with the bump portion.