A semiconductor device includes a semiconductor chip, which includes a substrate, a multilayer interconnect layer formed over the substrate, a first cell column disposed along an edge of the substrate in a plan view, the first cell column having a first I/O cell and a first power supply cell, second cell column disposed along the first cell column in plan view, the second cell column having a second I/O cell, a first pad supplying a first supply voltage to the first power supply cell, a first voltage supply wire disposed over the first cell column, a second voltage supply wire disposed over the second cell column, and a first connection wire crossing the first voltage supply wire and the second voltage supply wire.

Integrated circuit dies are provide with a passivation layer having a plurality of differently sized openings exposing bond pads for bonding. The sizes of the bond pads vary in a manner that at least partially compensates for stresses during bonding, such as flip chip thermocompression bonding, due to asymmetric distribution of bond pads.

In accordance with an embodiment of the present invention, a semiconductor device includes a first bond pad disposed at a first side of a substrate. The first bond pad includes a first plurality of pad segments. At least one pad segment of the first plurality of pad segments is electrically isolated from the remaining pad segments of the first plurality of pad segments.

A display device includes a substrate including a pad area, a first conductive pattern disposed in the pad area on the substrate, an insulating layer disposed on the first conductive pattern and overlapping the first conductive pattern, second conductive patterns disposed on the insulating layer, spaced apart from each other, and contacting the first conductive pattern through contact holes formed in the insulating layer, and a third conductive pattern disposed on the second conductive patterns and contacting the insulating layer.