Exemplary embodiments for redistribution layers of integrated circuit components are disclosed. The redistribution layers of integrated circuit components of the present disclosure include one or more arrays of conductive contacts that are configured and arranged to allow a bonding wave to displace air between the redistribution layers during bonding. This configuration and arrangement of the one or more arrays minimize discontinuities, such as pockets of air to provide an example, between the redistribution layers during the bonding.

A semiconductor structure includes an oval-shaped pad and a dielectric layer. The oval-shaped pad is on a substrate and includes a major axis corresponding to the largest distance of the oval-shaped pad. The major axis is toward a geometric center of the substrate. The dielectric layer covers the substrate and surrounds the oval-shaped pad.

Exemplary embodiments for redistribution layers of integrated circuit components are disclosed. The redistribution layers of integrated circuit components of the present disclosure include one or more arrays of conductive contacts that are configured and arranged to allow a bonding wave to displace air between the redistribution layers during bonding. This configuration and arrangement of the one or more arrays minimize discontinuities, such as pockets of air to provide an example, between the redistribution layers during the bonding.

A semiconductor device in chip size package includes first and second metal oxide semiconductor transistors both vertical transistors formed in first and second regions obtained by dividing the semiconductor device into halves. The first metal oxide semiconductor transistor includes one or more first gate electrodes and four or more first source electrodes provided in one major surface, each of the first gate electrodes is surrounded, in top view, by the first source electrodes, and for any combination of a first gate electrode and a first source electrode, closest points between the first gate and first source electrodes are on a line inclined to a chip side. The second metal oxide semiconductor transistor includes the same structure as the first metal oxide semiconductor transistor. A conductor that connects the drains of the first and second metal oxide semiconductor transistors is provided in the other major surface of the semiconductor device.

In an embodiment, a device includes: a first die array including first integrated circuit dies, orientations of the first integrated circuit dies alternating along rows and columns of the first die array; a first dielectric layer surrounding the first integrated circuit dies, surfaces of the first dielectric layer and the first integrated circuit dies being planar; a second die array including second integrated circuit dies on the first dielectric layer and the first integrated circuit dies, orientations of the second integrated circuit dies alternating along rows and columns of the second die array, front sides of the second integrated circuit dies being bonded to front sides of the first integrated circuit dies by metal-to-metal bonds and by dielectric-to-dielectric bonds; and a second dielectric layer surrounding the second integrated circuit dies, surfaces of the second dielectric layer and the second integrated circuit dies being planar.

The present application discloses a drive chip and a display panel. The drive chip includes a first area and a second area. The drive chip includes a substrate and drive pins. The density of the pins located in the first area is lower than the density of the pins located in the second area. The pins located in the second area includes first drive pins and second drive pins. The distance between the substrate and a face of the first drive pins away from the substrate is greater than the distance between the substrate and a face of the second drive pins away from the substrate. The occurrence of poor electric conduction is avoided.

The present disclosure provides a method of processing a semiconductor structure. The method includes: placing a first semiconductor structure inside a semiconductor processing apparatus; supplying a solution, wherein the solution is directed toward a surface of the first semiconductor structure, and the solution includes a solvent and a resist; rotating the first semiconductor structure to spread the solution over the surface of the first semiconductor structure; forming a resist layer on the surface of the first semiconductor structure using the resist in the solution; and removing a portion of the solvent from the solution by an exhaust fan disposed adjacent to a periphery of the first semiconductor structure.