An electronic device includes a substrate, first signal lines, pixel structures, first pads, transmission pads, a first combination circuit board, and a transmission circuit board. The first pads are electrically connected to some of a plurality of first signal lines. The transmission pads are electrically connected to some of the first signal lines. The first combination circuit board is disposed between a first side and a second side of the substrate opposite to each other. The transmission circuit board is disposed between the first combination circuit board and the second side of the substrate. The first combination circuit board is electrically connected to at least some of the first pads, and a first pitch exists between the adjacent first pads. The transmission pads are electrically connected to the transmission circuit board, and a transmission-pad pitch exists between the adjacent transmission pads. The transmission-pad pitch is greater than the first pitch.

Wirebond bondpads on semiconductor packages that result in reduced cross-talk and/or interference between vertical wires are disclosed. The vertical wirebonds may be disposed in the semiconductor package with stacked dies, where the wires are substantially normal to the bondpads to which the vertical wirebonds are attached on the dies. The wirebond bondpads may include signal pads that carry input/output (I/O) to/from the die package, as well as ground bondpads. The bondpads may have widths that are greater than the space between adjacent bondpads. Bondpads may be fabricated to be larger than the size requirements for reliable wirebond formation on the bondpads. For a fixed pitch bondpad configuration, the size of the signal bondpads adjacent to the ground bondpads may be greater than half of the pitch. By increasing the size of the signal bondpads adjacent to a ground line relative to the space therebetween, improved cross-talk performance may be achieved.

An electronic device includes a substrate, first signal lines, pixel structures, first pads, transmission pads, a first combination circuit board, and a transmission circuit board. The first pads are electrically connected to some of a plurality of first signal lines. The transmission pads are electrically connected to some of the first signal lines. The first combination circuit board is disposed between a first side and a second side of the substrate opposite to each other. The transmission circuit board is disposed between the first combination circuit board and the second side of the substrate. The first combination circuit board is electrically connected to at least some of the first pads, and a first pitch exists between the adjacent first pads. The transmission pads are electrically connected to the transmission circuit board, and a transmission-pad pitch exists between the adjacent transmission pads. The transmission-pad pitch is greater than the first pitch.

Wirebond bondpads on semiconductor packages that result in reduced cross-talk and/or interference between vertical wires are disclosed. The vertical wirebonds may be disposed in the semiconductor package with stacked dies, where the wires are substantially normal to the bondpads to which the vertical wirebonds are attached on the dies. The wirebond pads may include signal pads that carry input/output (I/O) to/from the die package, as well as ground bondpads. The vertical wirebond bondpads may have widths that are greater than the space between adjacent bondpads. Bondpads may be fabricated to be larger than the size requirements for reliable wirebond formation on the bondpads. For a fixed pitch bondpad configuration, the size of the signal bondpads adjacent to the ground bondpads may be greater than half of the pitch. By increasing the size (e.g., width) of the signal bondpads adjacent to a ground line relative to the space therebetween, improved cross-talk performance may be achieved.

An electronic device that includes a leadframe having contact pads, where at least two adjacent contact pads of the contact pads are disconnected from each other via a slot. A die includes input/output pins, where the input/output pins are connected to respective contact pads of the contact pads on the leadframe. Interconnects connect the input/output pins to the respective contact pads. A mold compound encapsulates the die and the interconnects.

Embodiments of the present application provide a display apparatus and a method for binding the same. The apparatus includes: a flexible display panel; and a chip on film bound on a binding region of the flexible display panel. The chip on film has at least two rows of output pads and the flexible display panel has at least two rows of input pads. Virtual elongation lines of all of the output pads intersect at a same intersection point in a first datum line perpendicular to the first direction. The output pads are electrically connected to the input pads and the output pads and the input pads have the virtual elongation lines at a same angle with respect to a common datum line, the common datum line being composed of the first datum line and the second datum line coinciding with each other.

Embodiments of the present application provide a display apparatus and a method for binding the same. The apparatus includes: a flexible display panel; and a chip on film bound on a binding region of the flexible display panel. The chip on film has at least two rows of output pads and the flexible display panel has at least two rows of input pads. Virtual elongation lines of all of the output pads intersect at a same intersection point in a first datum line perpendicular to the first direction. The output pads are electrically connected to the input pads and the output pads and the input pads have the virtual elongation lines at a same angle with respect to a common datum line, the common datum line being composed of the first datum line and the second datum line coinciding with each other.

A semiconductor package may include vertically-stacked semiconductor chips and first, second, and third connection terminals connecting the semiconductor chips to each other. Each of the semiconductor chips may include a semiconductor substrate, an interconnection layer on the semiconductor substrate, penetration electrodes connected to the interconnection layer through the semiconductor substrate, and first, second, and third groups on the interconnection layer. The interconnection layer may include an insulating layer and first and second metal layers in the insulating layer. The first and second groups may be in contact with the second metal layer, and the third group may be spaced apart from the second metal layer. Each of the first and third groups may include pads connected to a corresponding one of the first and third connection terminals in a many-to-one manner. The second group may include pads connected to the second connection terminal in a one-to-one manner.

A semiconductor package includes a first die having signal and dummy regions, and a second die on the first die. The first die includes first dummy patterns arranged in a first direction on the dummy region, second dummy patterns on the dummy region and between the first dummy patterns, a first dielectric layer on the first and second dummy patterns, and first pads extending through the first dielectric layer and coupled to the first dummy patterns. The second die includes second pads on the dummy region, and third pads on the dummy region. On an interface between the first and second dies, the first pads are in contact with the second pads. The first dielectric layer is between the second dummy patterns and the third pads. The first dummy patterns are connected to a ground circuit or power circuit of the first die.

A semiconductor package is provided. The semiconductor package includes: a first stack including a first semiconductor substrate; a through via that penetrates the first semiconductor substrate in a first direction; a second stack that includes a second face facing a first face of the first stack, on the first stack; a first pad that is in contact with the through via, on the first face of the first stack; a second pad including a concave inner side face that defines an insertion recess, the second pad located on the second face of the second stack; and a bump that connects the first pad and the second pad, wherein the bump includes a first upper bump on the first pad, and a first lower bump between the first upper bump and the first pad.