Provided is a display backplate including an array substrate and a plurality of pairs of connection structures on the array substrate, wherein the array substrate includes a plurality of thin-film transistors and a common electrode signal line, wherein at least one of the plurality of thin-film transistors is connected to one of a pair of connection structures and the common electrode signal line is connected to the other of the pair of connection structures; and an area of a first section of the connection structure is negatively correlated with a distance between the first section and a surface of the array substrate, and the first section is parallel to the surface of the array substrate.

A technique for fabricating a bump structure is disclosed. A substrate that includes a set of pads formed on a surface thereof is prepared, in which the pads includes first conductive material. A metallic adhesion layer is coated on each pad. A bump base is formed on each pad by sintering conductive particles using a mold layer, in which the conductive particles includes second conductive material different from the first conductive material.

A semiconductor package includes a first semiconductor chip including a first chip body portion and a first chip rear bump disposed in a region recessed into the first chip body portion, and a second semiconductor chip stacked on the first semiconductor chip and including a second chip body portion and a second chip front bump protruding from the second chip body portion. The first chip rear bump includes a lower metal layer and a solder layer disposed on the lower metal layer. The second chip front bump is bonded to the solder layer. The second chip front bump is disposed to cover at least the solder layer on a bonding surface of the second chip front bump and the solder layer.

A package structure includes a first die, a die stack structure bonded to the first die, a support structure and an insulation structure. The support structure is disposed on the die stack structure, and a sidewall of the support structure is laterally shifted from a sidewall of the die stack structure. The insulation structure is disposed on the first die and laterally wraps around the die stack structure and the support structure.

Embodiments of the present disclosure include semiconductor packages and methods of forming the same. An embodiment is a semiconductor package including a first package including one or more dies, and a redistribution layer coupled to the one or more dies at a first side of the first package with a first set of bonding joints. The redistribution layer including more than one metal layer disposed in more than one passivation layer, the first set of bonding joints being directly coupled to at least one of the one or more metal layers, and a first set of connectors coupled to a second side of the redistribution layer, the second side being opposite the first side.

The present disclosure relates to an integrated chip structure having a first substrate including a plurality of transistor devices disposed within a semiconductor material. An interposer substrate includes vias extending through a silicon layer. A copper bump is disposed between the first substrate and the interposer substrate. The copper bump has a sidewall defining a recess. Solder is disposed over the copper bump and continuously extending from over the copper bump to within the recess. A conductive layer is disposed between the first substrate and the interposer substrate and is separated from the copper bump by the solder.

Aspects of the invention include a method of tuning an interconnect that couples a first structure that is a first integrated circuit or a first laminate structure to a second structure that is a second integrated circuit or a second laminate structure. The method includes obtaining a compression requirement for a spring in a compliant layer of the interconnect. A longer path length of the spring leads to greater compression and mechanical support. Current and signal speed requirements for the interconnect are obtained. A shorter path length of the spring leads to greater current-carrying capacity and greater signal speed. Specifications for the spring are determined based on the compression requirement and the current and signal speed requirements. Determining the specifications includes determining a number of active coils of the spring to be less than two.

In an embodiment, a method includes: stacking a plurality of first dies to form a device stack; revealing testing pads of a topmost die of the device stack; testing the device stack using the testing pads of the topmost die; and after testing the device stack, forming bonding pads in the topmost die, the bonding pads being different from the testing pads.

A semiconductor package device includes a wiring structure, a semiconductor chip and an encapsulant. The semiconductor chip is electrically connected to the wiring structure. The encapsulant is disposed on the wiring structure and covers the semiconductor chip. A roughness (Ra) of a surface of the encapsulant is about 5 nm to about 50 nm.

A pillar structure, and a method of forming, for a substrate is provided. The pillar structure may have one or more tiers, where each tier may have a conical shape or a spherical shape. In an embodiment, the pillar structure is used in a bump-on-trace (BOT) configuration. The pillar structures may have circular shape or an elongated shape in a plan view. The substrate may be coupled to another substrate. In an embodiment, the another substrate may have raised conductive traces onto which the pillar structure may be coupled.