An apparatus, comprising an integrated circuit (IC) package having at least one solder bond pad, a die having at least one solder bond pad, wherein the die is bonded to the IC package by at least one solder joint between the at least one solder bond pad of the die, and the at least one solder bond pad of the IC package, and an underfill material between the IC package and the die, wherein the at least one solder joint is embedded in the underfill material, and wherein the at least one solder joint comprises a first metallurgy and a second metallurgy.

An apparatus, comprising an integrated circuit (IC) package having at least one solder bond pad, a die having at least one solder bond pad, wherein the die is bonded to the IC package by at least one solder joint between the at least one solder bond pad of the die, and the at least one solder bond pad of the IC package, and an underfill material between the IC package and the die, wherein the at least one solder joint is embedded in the underfill material, and wherein the at least one solder joint comprises a first metallurgy and a second metallurgy.

Provided is a composition for conductive adhesive. The composition for conductive adhesive includes a heterocyclic compound containing oxygen and including at least one of an epoxy group or oxetane group, a reductive curing agent including an amine group and a carboxyl group, and a photoinitiator, wherein a mixture ratio of the heterocyclic compound and the reductive curing agent satisfies Conditional Expression 1 below.

0.5≤(b+c)/a≤1.5, a>0, b≥0, c>0  [Conditional Expression 1] where ‘a’ denotes a mole number of a heterocycle in the heterocyclic compound, ‘b’ denotes a mole number of hydrogen bonded to a nitrogen atom of the amine group included in the reductive curing agent, and ‘c’ denotes a mole number of the carboxyl group.

Provided is a composition for conductive adhesive. The composition for conductive adhesive includes a heterocyclic compound containing oxygen and including at least one of an epoxy group or oxetane group, a reductive curing agent including an amine group and a carboxyl group, and a photoinitiator, wherein a mixture ratio of the heterocyclic compound and the reductive curing agent satisfies Conditional Expression 1 below.

0.5≤(b+c)/a≤1.5, a>0, b≥0, c>0  [Conditional Expression 1] where ‘a’ denotes a mole number of a heterocycle in the heterocyclic compound, ‘b’ denotes a mole number of hydrogen bonded to a nitrogen atom of the amine group included in the reductive curing agent, and ‘c’ denotes a mole number of the carboxyl group.

Various embodiments of the present application are directed towards a method for forming an integrated chip in which a group III-V device is bonded to a substrate, as well as the resulting integrated chip. In some embodiments, the method includes: forming a chip including an epitaxial stack, a metal structure on the epitaxial stack, and a diffusion layer between the metal structure and the epitaxial stack; bonding the chip to a substrate so the metal structure is between the substrate and the epitaxial stack; and performing an etch into the epitaxial stack to form a mesa structure with sidewalls spaced from sidewalls of the diffusion layer. The metal structure may, for example, be a metal bump patterned before the bonding or may, for example, be a metal layer that is on an etch stop layer and that protrudes through the etch stop layer to the diffusion layer.

Various embodiments of the present application are directed towards a method for forming an integrated chip in which a group III-V device is bonded to a substrate, as well as the resulting integrated chip. In some embodiments, the method includes: forming a chip including an epitaxial stack, a metal structure on the epitaxial stack, and a diffusion layer between the metal structure and the epitaxial stack; bonding the chip to a substrate so the metal structure is between the substrate and the epitaxial stack; and performing an etch into the epitaxial stack to form a mesa structure with sidewalls spaced from sidewalls of the diffusion layer. The metal structure may, for example, be a metal bump patterned before the bonding or may, for example, be a metal layer that is on an etch stop layer and that protrudes through the etch stop layer to the diffusion layer.

A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes: a semiconductor chip; a substrate facing an active surface of the semiconductor chip; and a conductive bump extending from the active surface of the semiconductor chip toward the substrate, wherein the conductive bump comprises: a plurality of bump segments comprising a first group of bump segments and a second group of bump segments, wherein each bump segment comprises the same segment height in a direction orthogonal to the active surface of the semiconductor chip, and each bump segment comprises a volume defined by the multiplication of the segment height with the average cross-sectional area of the bump segment; wherein the ratio of the total volume of the first group of bump segments to the total volume of the second group of bump segments is between about 0.03 and about 0.8.

A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes: a semiconductor chip; a substrate facing an active surface of the semiconductor chip; and a conductive bump extending from the active surface of the semiconductor chip toward the substrate, wherein the conductive bump comprises: a plurality of bump segments comprising a first group of bump segments and a second group of bump segments, wherein each bump segment comprises the same segment height in a direction orthogonal to the active surface of the semiconductor chip, and each bump segment comprises a volume defined by the multiplication of the segment height with the average cross-sectional area of the bump segment; wherein the ratio of the total volume of the first group of bump segments to the total volume of the second group of bump segments is between about 0.03 and about 0.8.

The present disclosure provides methods to integrate piezoelectric micromachined ultrasonic transducer (pMUT) arrays with an application-specific integrated circuit (ASIC) using thermocompression or eutectic/solder bonding. In an aspect, the present disclosure provides a device comprising a first substrate and a second substrate, the first substrate comprising a pMUT array and the second substrate comprising an electrical circuit, wherein the first substrate and the second substrate are bonded together using thermocompression, wherein any set of individual PMUTs of PMUT array is addressable. In another aspect, the present disclosure provides a device comprising a first substrate and a second substrate, the first substrate comprising a pMUT array and the second substrate comprising an electrical circuit, wherein the first substrate and the second substrate are bonded together using eutectic or solder bonding, wherein any set of individual PMUTs of the PMUT array is addressable.

The present disclosure provides methods to integrate piezoelectric micromachined ultrasonic transducer (pMUT) arrays with an application-specific integrated circuit (ASIC) using thermocompression or eutectic/solder bonding. In an aspect, the present disclosure provides a device comprising a first substrate and a second substrate, the first substrate comprising a pMUT array and the second substrate comprising an electrical circuit, wherein the first substrate and the second substrate are bonded together using thermocompression, wherein any set of individual PMUTs of PMUT array is addressable. In another aspect, the present disclosure provides a device comprising a first substrate and a second substrate, the first substrate comprising a pMUT array and the second substrate comprising an electrical circuit, wherein the first substrate and the second substrate are bonded together using eutectic or solder bonding, wherein any set of individual PMUTs of the PMUT array is addressable.