Patent classifications
H01L2224/13191
SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF
A semiconductor package and a method of manufacturing a semiconductor package. As a non-limiting example, various aspects of this disclosure provide a semiconductor package, and a method of manufacturing thereof, that comprises a first semiconductor die, a plurality of adhesive regions spaced apart from each other on the first semiconductor die, and a second semiconductor die adhered to the plurality of adhesive regions.
Semiconductor structure and manufacturing method thereof
A semiconductor structure includes a substrate; a pad disposed over the substrate; a passivation disposed over the substrate and exposing a portion of the pad; and a bump disposed over the portion of the pad. The bump includes a buffering member disposed over the portion of the pad; and a conductive layer surrounding the buffering member and electrically connected to the pad.
Semiconductor structure and manufacturing method thereof
A semiconductor structure includes a substrate; a pad disposed over the substrate; a passivation disposed over the substrate and exposing a portion of the pad; and a bump disposed over the portion of the pad. The bump includes a buffering member disposed over the portion of the pad; and a conductive layer surrounding the buffering member and electrically connected to the pad.
Semiconductor device arrangement with compressible adhesive
A method of forming a semiconductor package includes providing a first metal substrate; and mounting a stacked arrangement on the first metal substrate, the stacked arrangement comprising a semiconductor die, wherein mounting the stacked arrangement includes: providing a first layer of attachment material between the first metal substrate and the stacked arrangement; and providing a second layer of attachment material within the stacked arrangement at an interface with the semiconductor die, wherein at least one of the first and second layers of attachment material is a compressible layer that includes one or more elastomeric elements embedded within a matrix of solder material.
INTEGRATED CIRCUIT (IC) WITH EXPOSED ACTIVE CIRCUITRY
In one example, a method can include forming a mask layer on a first surface of a first wafer, forming a pattern in the mask layer to expose areas of the first wafer through the mask layer, and removing a substrate layer from the first wafer from the exposed areas of the first surface of the first wafer to expose a second layer of the first wafer or to expose dies. In another example, a method can include providing a cap over an area on a surface of a die bonded to and spaced apart from the surface of the die by a spacer, applying mold compound to encapsulate the die and at least a portion of the cap such that a surface of the cap remains unencapsulated, and removing at least a portion of a layer from the cap over the area of the die.