A system and method for preventing cracks is provided. An embodiment comprises placing crack stoppers into a connection between a semiconductor die and a substrate. The crack stoppers may be in the shape of hollow or solid cylinders and may be placed so as to prevent any cracks from propagating through the crack stoppers.

A semiconductor package structure includes a semiconductor die surface having a narrower pitch region and a wider pitch region adjacent to the narrower pitch region, a plurality of first type conductive pillars in the narrower pitch region, each of the first type conductive pillars having a copper-copper interface, and a plurality of second type conductive pillars in the wider pitch region, each of the second type conductive pillars having a copper-solder interface. A method for manufacturing the semiconductor package structure described herein is also disclosed.

A semiconductor package structure includes a semiconductor die surface having a narrower pitch region and a wider pitch region adjacent to the narrower pitch region, a plurality of first type conductive pillars in the narrower pitch region, each of the first type conductive pillars having a copper-copper interface, and a plurality of second type conductive pillars in the wider pitch region, each of the second type conductive pillars having a copper-solder interface. A method for manufacturing the semiconductor package structure described herein is also disclosed.

Provided are a Cu column, a Cu core column, a solder joint, and a through-silicon via, which have the low Vickers hardness and the small arithmetic mean roughness. For the Cu column 1 according to the present invention, its purity is equal to or higher than 99.9% and equal to or lower than 99.995%, its arithmetic mean roughness is equal to or less than 0.3 μm, and its Vickers hardness is equal to or higher than 20 HV and equal to or less than 60 HV. Since the Cu column 1 is not melted at a melting temperature in the soldering and a definite stand-off height (a space between the substrates) can be maintained, it is preferably applied to the three dimensional mounting or the pitch narrowing mounting.

A device (2) is formed on a main surface of a substrate (1). The main surface of the substrate (1) is bonded to the undersurface of the counter substrate (14) via the bonding member (11,12,13) in a hollow state. A circuit (17) and a bump structure (26) are formed on the top surface of the counter substrate (14). The bump structure (26) is positioned in a region corresponding to at least the bonding member (11,12,13), and has a higher height than that of the circuit (17).

A Cu core ball and a method of manufacturing such a Cu core ball. Purity of the Cu internal ball is at least 99.9% and not greater than 99.995%. A total contained amount of Pb and/or Bi in impurity contained in the Cu ball is equal to or larger than 1 ppm. Its sphericity is at least 0.95. A solder plating film coated on the Cu ball is of Sn solder or a lead free solder alloy whose primary component is Sn. In the solder plating film, a contained amount of U is not more than 5 ppb and that of Th is not more than 5 ppb. A total alpha dose of the Cu ball and the solder plating film is not more than 0./0200 cph/cm2. An arithmetic average roughness of the Cu core ball is equal to or less than 0.3 μm.

A manufacturing method comprises preparing a bonding substrate having bumps thereon; preparing a mounted member having external conductive members; applying a fixing material to the surface of the bonding substrate and/or to a surface of the mounted member; and fixing the bonding substrate and the mounted member with the fixing material such that the bumps contact the external conductive members. The fixing material is prepared to contain a first compound and a second compound, each having respective viscosities which change depending on their respective temperature profiles; and applying the fixing material to the bonding substrate and/or the mounted member at a temperature lower than a first temperature, and the fixing comprises pressing the bonding substrate against the mounted member when the fixing material has a temperature lower than the first temperature; and heating the fixing material to a temperature higher than the second temperature and curing the fixed material.

Semiconductor devices are described that have bump assemblies configured to furnish shock absorber functionality. In an implementation, a wafer-levelchip-scale package devices include an integrated circuit chip having an array of bump assemblies disposed over the integrated circuit chip. The array of bump assemblies comprises a plurality of first bump assemblies that include solder bumps composed at least substantially of a solder composition (i.e., solder bumps that do not include a core). The array further comprises a plurality of second bump assemblies that includes a solder bump having a core configured to furnish shock absorber functionality to the integrated circuit chip.

A metal pillar with cushioned tip is disclosed. The cushioned tip offsets height difference among metal pillars. So that the height difference among metal pillars gives no significant effect to electrical coupling. The cushioned tip is a metal sponge. Additional one embodiment shows a second metal is plated on a tip of the metal sponge. A hardness of the second metal is greater than a hardness of a metal of the metal sponge, so that the second metal can stab into a corresponding metal sponge for electrical coupling.

Provided is a solder material which enables a growth of an oxide film to be inhibited. A solder ball which is a solder material is composed of a solder layer and a covering layer covering the solder layer. The solder layer is spherical and is composed of a metal material containing an alloy including Sn content of 40% and more. Otherwise the solder layer is composed of a metal material including Sn content of 100%. In the covering layer, a S.sub.nO film is formed outside the solder layer, and a S.sub.nO.sub.2 film is formed outside the S.sub.nO film. A thickness of the covering layer is preferably more than 0 nm and equal to or less than 4.5 nm. Additionally, a yellow chromaticity of the solder ball is preferably equal to or less than 5.7.