A surface mount structure includes a substrate, a sensor, an electrical contact and a package body. The substrate has a first surface and a second surface opposite to the first surface. The sensor is disposed adjacent to the second surface of the substrate. The electrical contact is disposed on the first surface of the substrate. The package body covers the first surface and the second surface of the substrate, a portion of the sensor and a first portion of the electrical contact.

A semiconductor package includes a first substrate, a first bonding pad on the first substrate, a solder ball on the first bonding pad, and a blocking layer on the solder ball, wherein a thickness of the blocking layer varies in a direction away from the first substrate.

A method includes aligning a first electrical connector of a first package component to a second electrical connector of a second package component. With the first electrical connector aligned to the second electrical connector, a metal layer is plated on the first and the second electrical connectors. The metal layer bonds the first electrical connector to the second electrical connector.

A resin-encapsulated semiconductor device includes a bump electrode formed on an element surface side of a semiconductor chip, a conductive layer electrically connected to the bump electrode, and a resin encapsulation body covering the semiconductor chip, the bump electrode, and the conductive layer. On a back surface of the semiconductor chip that is flush with a back surface of the resin encapsulation body, a metal layer and a laminated film are formed. The laminated film is formed on a front surface of the conductive layer, and an external terminal is arranged on an inner side of an outer edge of the semiconductor chip.

A method providing a high aspect ratio through substrate via in a substrate is described. The through substrate via has vertical sidewalls and a horizontal bottom. The substrate has a horizontal field area surrounding the through substrate via. A first metallic barrier layer is deposited on the sidewalls of the through substrate via. A nitridation process converts a surface portion of the metallic barrier layer to a nitride surface layer. The nitride surface layer enhances the nucleation of subsequent depositions. A first metal layer is deposited to fill the through substrate via. A selective etch creates a recess in the first metal layer in the through substrate via. A second barrier layer is deposited over the recess. A second metal layer is patterned over the second barrier layer filling the recess and creating a contact. Another aspect of the invention is a device produced by the method.

An advanced through silicon via structure for is described. The device includes a substrate including integrated circuit devices. A high aspect ratio through substrate via is disposed in the substrate. The through substrate via has vertical sidewalls and a horizontal bottom. The substrate has a horizontal field area surrounding the through substrate via. A metallic barrier layer is disposed on the sidewalls of the through substrate via. A surface portion of the metallic barrier layer has been converted to a nitride surface layer by a nitridation process. The nitride surface layer enhances the nucleation of subsequent depositions. A first metal layer fills the through substrate via and has a recess in an upper portion. A second barrier layer is disposed over the recess. A second metal layer is disposed over the second barrier layer and creates a contact.

The resin-encapsulated semiconductor device includes a bump electrode (2) formed on an element surface side of a semiconductor chip (1), a conductive layer (3) electrically connected to the bump electrode (2), and a resin encapsulation body (6) covering the semiconductor chip (1), the bump electrode (2), and the conductive layer (3). On a back surface of the semiconductor chip (1) that is flush with a back surface of the resin encapsulation body (6), a metal layer (4) and a laminated film (5) are formed. The laminated film (5) is formed on a front surface of the conductive layer (3). The external terminal (9) is arranged on an inner side of an outer edge of the semiconductor chip (1).

Embodiments include semiconductor packages and a method of forming the semiconductor packages. A semiconductor package includes a resist layer disposed on a conductive layer. The semiconductor package also has a bump disposed on the conductive layer. The bump has a top surface and one or more sidewalls. The semiconductor package further includes a surface finish disposed on the top surface and the one or more sidewalls of the bump. The semiconductor package may have the surface finish surround the top surface and sidewalls of the bumps to protect the bumps from Galvanic corrosion. The surface finish may include a nickel-palladium-gold (NiPdAu) surface finish. The semiconductor package may also have a seed disposed on a top surface of the resist layer, and a dielectric disposed on the seed. The dielectric may surround the sidewalls of the bump. The semiconductor package may include the seed to be an electroless copper seed.

Embodiments include semiconductor packages and a method of forming the semiconductor packages. A semiconductor package includes a resist layer disposed on a conductive layer. The semiconductor package also has a bump disposed on the conductive layer. The bump has a top surface and one or more sidewalls. The semiconductor package further includes a surface finish disposed on the top surface and the one or more sidewalls of the bump. The semiconductor package may have the surface finish surround the top surface and sidewalls of the bumps to protect the bumps from Galvanic corrosion. The surface finish may include a nickel-palladium-gold (NiPdAu) surface finish. The semiconductor package may also have a seed disposed on a top surface of the resist layer, and a dielectric disposed on the seed. The dielectric may surround the sidewalls of the bump. The semiconductor package may include the seed to be an electroless copper seed.

A semiconductor package device includes a carrier, a first electronic component, and a conductive element on the carrier. The first electronic component is over the carrier. The conductive element is on the carrier and electrically connects the first electronic component to the carrier. The conductive element includes at least one conductive particle and a solder material covering the conductive particle, and the conductive particle includes a metal core, a barrier layer covering the metal core, and a metal layer covering the barrier layer.