Patent classifications
H
ELECTRICITY
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H01
ELECTRIC ELEMENTS
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H01L
SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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2224/00
Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
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H01L2224/01
Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
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H01L2224/10
Bump connectors; Manufacturing methods related thereto
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H01L2224/12
Structure, shape, material or disposition of the bump connectors prior to the connecting process
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H01L2224/14
of a plurality of bump connectors
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H01L2224/1414
Circular array, i.e. array with radial symmetry
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H01L2224/14141
being uniform, i.e. having a uniform pitch across the array
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H01L2224/14141

Method and System for Packing Optimization of Semiconductor Devices
20180047692 · 2018-02-15 ·

Provided is a disclosure for optimizing the number of semiconductor devices on a wafer/substrate. The optimization comprises laying out, cutting, and packaging the devices efficiently.