A semiconductor chip is mounted on a mounting substrate. The semiconductor chip includes plural first bumps on a surface facing the mounting substrate. The plural first bumps each have a shape elongated in a first direction in plan view and are arranged in a second direction perpendicular to the first direction. The mounting substrate includes, on a surface on which the semiconductor chip is mounted, at least one first land connected to the plural first bumps. At least two first bumps of the plural first bumps are connected to each first land. The difference between the dimension of the first land in the second direction and the distance between the outer edges of two first bumps at respective ends of the arranged first bumps connected to the first land is 20 μm or less.

A semiconductor chip is mounted on a mounting substrate. The semiconductor chip includes plural first bumps on a surface facing the mounting substrate. The plural first bumps each have a shape elongated in a first direction in plan view and are arranged in a second direction perpendicular to the first direction. The mounting substrate includes, on a surface on which the semiconductor chip is mounted, at least one first land connected to the plural first bumps. At least two first bumps of the plural first bumps are connected to each first land. The difference between the dimension of the first land in the second direction and the distance between the outer edges of two first bumps at respective ends of the arranged first bumps connected to the first land is 20 μm or less.

A method of forming semiconductor device includes forming interconnect structure over substrate; forming first passivation layer over the interconnect structure, and metal-insulator-metal capacitor in the first passivation layer; forming first redistribution layer including first pads over the first passivation layer, and first vias extending into the first passivation layer; conformally forming second passivation layer over the first redistribution layer and first passivation layer, and patterning the second passivation layer to form via openings exposing the first pads; forming second redistribution layer including second pads over the second passivation layer, and second vias in the first via openings, wherein the first and second redistribution layers include aluminum-copper alloy and copper, respectively; forming dielectric layer over the second redistribution layer, and patterning the dielectric layer to form via openings exposing some second pads; and forming bumps over the dielectric layer and in the via openings to contact exposed second pads.

Within a layout of a first surface in a flip chip configuration, a bump restriction area is mapped according to a set of bump placement restrictions, wherein a first bump placement restriction specifies an allowed distance range between a bump and a qubit chip element in a layout of the first surface in the flip chip configuration. An electrically conductive material is deposited outside the bump restriction area, to form the bump, wherein the bump comprises an electrically conductive structure that electrically couples a signal from the first surface and is positioned according to the set of bump placement restrictions.

The present disclosure provides a display panel and a display device. The display panel includes a display region and a non-display region. The non-display region includes a first driving chip bonding region. The first driving chip bonding region includes a substrate and at least two rows of first pins formed on the substrate along a first direction, each row of the first pins includes at least two of the first pins formed along a second direction. Thicknesses of the first pins formed near the display region are greater than thicknesses of the first pins formed far from the display region.

A lateral power semiconductor device with a metal interconnect layout for low on-resistance. The metal interconnect layout includes first, second, and third metal layers, each of which include source bars and drain bars. Source bars in the first, second, and third metal layers are electrically connected. Drain bars in the first, second, and third metal layers are electrically connected. In one embodiment, the first and second metal layers are parallel, and the third metal layer is perpendicular to the first and second metal layers. In another embodiment, the first and third metal layer are parallel, and the second metal layer is perpendicular to the first and third metal layers. A nonconductive layer ensures solder bumps electrically connect to only source bars or only drain bars. As a result, a plurality of available pathways exists and enables current to take any of the plurality of available pathways.

A lateral power semiconductor device with a metal interconnect layout for low on-resistance. The metal interconnect layout includes first, second, and third metal layers, each of which include source bars and drain bars. Source bars in the first, second, and third metal layers are electrically connected. Drain bars in the first, second, and third metal layers are electrically connected. In one embodiment, the first and second metal layers are parallel, and the third metal layer is perpendicular to the first and second metal layers. In another embodiment, the first and third metal layer are parallel, and the second metal layer is perpendicular to the first and third metal layers. A nonconductive layer ensures solder bumps electrically connect to only source bars or only drain bars. As a result, a plurality of available pathways exists and enables current to take any of the plurality of available pathways.

A semiconductor module includes a laminated substrate having an insulating plate, a circuit pattern on an upper surface of the insulating plate and a heat dissipating plate on a lower surface of the insulating plate. The module further includes a semiconductor device having upper and lower surfaces, and including a collector electrode on the device upper surface, an emitter electrode and a gate electrode on the device lower surface, and the emitter electrode and the gate electrode each being bonded to an upper surface of the circuit pattern via a bump, and a block electrode bonded to the collector electrode. The block electrode includes a flat plate portion covering over the semiconductor device, and a pair of projecting portions projecting toward the circuit pattern from both ends of the flat plate portion in a thickness direction orthogonal to a surface of the insulating plate, and being bonded to the circuit pattern.

A passive micro light-emitting diode matrix device with uniform luminance includes a micro light-emitting diode matrix including a plurality of micro light-emitting matrices, each of which includes a first layer, a plurality of light-emitting layers disposed on the first layer, a plurality of second layers disposed on the light-emitting layers, respectively, a plurality of first inner electrode layers disposed on the second layers, respectively, and a second inner electrode layer which is disposed on the first layer, and which includes a first portion and a second portion having a plurality of through holes to accommodate said light-emitting layers, respectively.

A passive micro light-emitting diode matrix device with uniform luminance includes a micro light-emitting diode matrix including a plurality of micro light-emitting matrices, each of which includes a first layer, a plurality of light-emitting layers disposed on the first layer, a plurality of second layers disposed on the light-emitting layers, respectively, a plurality of first inner electrode layers disposed on the second layers, respectively, and a second inner electrode layer which is disposed on the first layer, and which includes a first portion and a second portion having a plurality of through holes to accommodate said light-emitting layers, respectively.