Provided is a disclosure for optimizing the number of semiconductor devices on a wafer/substrate. The optimization comprises laying out, cutting, and packaging the devices efficiently.

A method of manufacturing a semiconductor device may include forming an adhesive film on a surface of a semiconductor chip, mounting the semiconductor chip on a substrate such that the adhesive film contacts an upper surface of the substrate, and bonding the semiconductor chip and the substrate curing the adhesive film by simultaneously performing a thermo-compression process and an ultraviolet irradiation process on the adhesive film disposed between the substrate and the semiconductor chip.

A chip structure including a chip body and a plurality of conductive bumps. The chip body includes an active surface and a plurality of bump pads disposed on the active surface. The conductive bumps are disposed on the active surface of the chip body and connected to the bump pads respectively, and at least one of the conductive bumps has a trapezoid shape having one pair of parallel sides and one pair of non-parallel sides.

Within a layout of a first surface in a flip chip configuration, a bump restriction area is mapped according to a set of bump placement restrictions, wherein a first bump placement restriction specifies an allowed distance range between a bump and a qubit chip element in a layout of the first surface, and wherein a second bump placement restriction specifies an allowed distance range between the bump and a qubit chip element in a layout of a second surface in the flip chip configuration. An electrically conductive material is deposited outside the bump restriction area, to form the bump, wherein the bump comprises an electrically conductive structure that electrically couples a signal between the first surface and the second surface and is positioned according to the set of bump placement restrictions.

A driving chip and a display device are provided herein. The driving chip includes a substrate, a plurality of connection bumps and a plurality of buffer bumps on the substrate. Each of the connection bumps and the buffer bumps is disposed on a first substrate of the substrate. The buffer bump includes a first end face with a height a, and the connection bump has a connection bump end face with a height b, a<b. The height is a distance from a corresponding end face of the connection bump or the buffer bump to the first surface. With the buffer bumps on the driving chip, stress buffering can be achieved, which can further improve the bonding effect of the driving chip.

A driving chip and a display device are provided herein. The driving chip includes a substrate, a plurality of connection bumps and a plurality of buffer bumps on the substrate. Each of the connection bumps and the buffer bumps is disposed on a first substrate of the substrate. The buffer bump includes a first end face with a height a, and the connection bump has a connection bump end face with a height b, a<b. The height is a distance from a corresponding end face of the connection bump or the buffer bump to the first surface. With the buffer bumps on the driving chip, stress buffering can be achieved, which can further improve the bonding effect of the driving chip.

A semiconductor device assembly that includes a substrate having a first side and a second side, the first side having at least one dummy pad and at least one electrical pad. The semiconductor device assembly includes a first semiconductor device having a first side and a second side and at least one electrical pillar extending from the second side. The electrical pillar is connected to the electrical pad via solder to form an electrical interconnect. The semiconductor device assembly includes at least one dummy pillar extending from the second side of the first semiconductor device and a liquid positioned between an end of the dummy pillar and the dummy pad. The surface tension of the liquid pulls the dummy pillar towards the dummy pad. The surface tension may reduce or minimize a warpage of the semiconductor device assembly and/or align the dummy pillar and the dummy pad.

Provided is a disclosure for optimizing the number of semiconductor devices on a wafer/substrate. The optimization comprises laying out, cutting, and packaging the devices efficiently.

A chip structure including a chip body and a plurality of conductive bumps. The chip body includes an active surface and a plurality of bump pads disposed on the active surface. The conductive bumps are disposed on the active surface of the chip body and connected to the bump pads respectively, and at least one of the conductive bumps has a trapezoid shape having one pair of parallel sides and one pair of non-parallel sides.

A stacked memory device includes: a plurality of semiconductor chips that are stacked and transfer signals through a plurality of through-electrodes, wherein at least one of the semiconductor chips comprises: a re-timing circuit suitable for receiving input signals and first and second clocks, performing a re-timing operation of latching the input signals based on the second clock to output re-timed signals, and reflecting a delay time of the re-timing operation into the first clock to output a replica clock; and a transfer circuit suitable for transferring the re-timed signals to the through-electrodes based on the replica clock.